From patchwork Tue Jun 13 00:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Edgecombe X-Patchwork-Id: 13277738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AD68C7EE2E for ; Tue, 13 Jun 2023 00:13:04 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 3D8358E0018; Mon, 12 Jun 2023 20:12:32 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 338028E000B; Mon, 12 Jun 2023 20:12:32 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 13D238E0018; Mon, 12 Jun 2023 20:12:32 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id E553F8E000B for ; Mon, 12 Jun 2023 20:12:31 -0400 (EDT) Received: from smtpin21.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id B7AF71203A0 for ; Tue, 13 Jun 2023 00:12:31 +0000 (UTC) X-FDA: 80895798102.21.F79CD5A Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by imf08.hostedemail.com (Postfix) with ESMTP id 21B8C16001F for ; Tue, 13 Jun 2023 00:12:28 +0000 (UTC) Authentication-Results: imf08.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=JPrJdNqc; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf08.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 134.134.136.65 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1686615149; a=rsa-sha256; cv=none; b=htEa0gpUpU1PP+aONLndSKs54Oo/ci0fo/MFtJmKuAio1MJ0azZ+O66SBvF6XUxm4IAQxt wCjMnzMKpDi6XRJjNwsnr9wrSnSNXe+X9wKefFeBJ+dKK/Axg/5Ih/1MuGWi/GggsE022G 2nZRXkUXHJ2Rm15Hpm0g9qT5n+TxOeA= ARC-Authentication-Results: i=1; imf08.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=JPrJdNqc; dmarc=pass (policy=none) header.from=intel.com; spf=pass (imf08.hostedemail.com: domain of rick.p.edgecombe@intel.com designates 134.134.136.65 as permitted sender) smtp.mailfrom=rick.p.edgecombe@intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1686615149; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=ngsNHJkwJ8rpoiE9+OlXKRzL3wHKwvwi/lLZa6Im/hc=; b=FCtQ8POPmvwFYoLISgUtATZlamqmXBIQXQ76dsqUHyy2Wkegr3TZiQ89P/STAfIl8d4P49 kaYVlqcKoDxRQ9gTZHRlxoHmYuZkEb+zoyIy0M1EGu04zWC9NU4KNviWvLWT/fDqjf07hh xv2B1W42ic7wQE1NB+6rK+eZzq/2J/Q= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686615149; x=1718151149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QMw9iVo5bgNcqwrdr19MOUpW+koohCohKti/401XfIw=; b=JPrJdNqcBodz9lL6K9CvDGG0Mb94roKf0lSeHyauFbErtdMGpeHH9+hK hiMaacwvhz+4wPDu1OztkRNnwb+TptCDJa1GSSrpmAQTcSAKDFagkuHKt 7R5g69mgVmZV9JQCXqoOoeLvOOqoZ/DRpen45BEXk1gCpq79YqIcMxcPs 0c/i2U4b6lyy2c58YP68B6A5UPnbk7wtYIvc32fV6AnP0qLW7+1QYDx40 CN9DoXEGQP27Xj36JFKpfvbythUFpxdRxTw7QjcT6e5muZvGG3amVA/gs Q+NZowMWi+Fr6xHRKuAARopZsvbELZ3K+PmaQecDXAWLqSWP+x5NaFmEk Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="361557206" X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="361557206" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2023 17:12:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="835671062" X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="835671062" Received: from almeisch-mobl1.amr.corp.intel.com (HELO rpedgeco-desk4.amr.corp.intel.com) ([10.209.42.242]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2023 17:12:27 -0700 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, david@redhat.com, debug@rivosinc.com, szabolcs.nagy@arm.com, torvalds@linux-foundation.org, broonie@kernel.org Cc: rick.p.edgecombe@intel.com, Yu-cheng Yu , Pengfei Xu Subject: [PATCH v9 23/42] Documentation/x86: Add CET shadow stack description Date: Mon, 12 Jun 2023 17:10:49 -0700 Message-Id: <20230613001108.3040476-24-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613001108.3040476-1-rick.p.edgecombe@intel.com> References: <20230613001108.3040476-1-rick.p.edgecombe@intel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 21B8C16001F X-Stat-Signature: nxh16a8cue8dh4r3ty58qr7zxta71rtj X-HE-Tag: 1686615148-433028 X-HE-Meta: U2FsdGVkX1+KPlXf4hYBTa4uy2IfQGlvIr7v0RYgMaFZtlfjpHtQENZjz7DayFRQser08J1BsWYKrxc/folkmq3ZUCq4+Jb2pU783f82VMxrL6NUX779uagz5ROhzEZ2BuxXEwS6vj6i5X+1h0i824gFD1w74Sb5OYNHgv9wtuNUzZB8xGFkatuFNMCb8k9Pwx6bOQ/lrACSBC8dR5VOnZSJPHw/LJasMUbNOcOwgXwEpysp4WThz6vLrOuESkpoJp4HTOkDJbnWla07y0A/aWqD0AtbCSUn/FMRl1GHQd8D9Noz6ixnAvnyc5dl/Og0hAJ303N6lsbeIgsMquP7foTWfbe53MwEyAM6JhGO3vCaSRI12wY09GP0wfCTu+ijZio1d8NZBh1JZC8MoRii+rB2F0MQdjSQm/jS6kgSDabyKn0YundVPUQixilHW++F7kofJ07LpNjqZfUGZ4u5DmWmNtKr2eL0nMNw0uK46xOLjISukr1mQORy7tn6d2qxSwpLdR/nFTUyUVU+NYokkA7smWz/0DqtQ7a4HFcXRAW1ocW5CybTCvYa5ahrZGXex7zZXIq2mit30OA4A4hNYgHB1DO29YFowz+nZLsz3CCrs7ClBHGB66Dq8vAEMpMZLfTBVoDH9tODeAn3EIO0Zv+TSfL/BaF8cedXvw5rVjxTFtcZKMRBuJXRpYaws4f+cz0jiHziLuo9qi3UepgNwBUyXfV+eL0uBugZKwjI0csnHxLL1iK+Cu9IvcUbrmRfm77e+fPjT6g/u22xagD+SJihqoLjZ0Mu5sm0XGUiMbx3u7N7vRPpJeO1RS6F0zNLHxPR6ONa45Eh6mIDJwDZjJpll2uUH05gm5kR8/+waL4aXS51Dgyy5Cyok9+GI8/f4JRmpUsVfoEiBSD/K3MvwgnLszpKYAG9scaWeVRXjDtj3lpl794aMY+Pd3IfYSrszwrm8+Rn7zgpLOhG7uz ute+QNZk yXHd6/4lcEbaQrgKMYvYbbBdjIhO9ZSnXLcmJPmg1Fmx/HPOi6qC6fa5fSQ0MCz4YbVDC+TXrJlEZlGTHahFUgJ3LdYd1i7Ycp5+J5hbMJLOPptgup95B+lqGaRTddmq1JIGwqX0fdGtsY/vKPrNWFZ/Moxk9Mrl3I1t+jhlg73JqeukC0vgi9WuY4zV9vBPIQrsW0/94qT1cgyIY8MgXXHz0wmMrwc9V54CuyZEg+dsxcV4f+AYClJYw7u6RPGb5i5ePAma1v6u+xLDaWIqpFfjO69K4MALgMoGGIxoWD+RgC5Y0zgEBGsVgq7fTKzrTbDOQaSTTAw9ChHz5vAJiBb6Cf1/b3ri7HGcLs+YjF49OXGgAJON+I9Dc7A== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Introduce a new document on Control-flow Enforcement Technology (CET). Co-developed-by: Yu-cheng Yu Signed-off-by: Yu-cheng Yu Signed-off-by: Rick Edgecombe Reviewed-by: Borislav Petkov (AMD) Reviewed-by: Kees Cook Acked-by: Mike Rapoport (IBM) Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Reviewed-by: Szabolcs Nagy --- Documentation/arch/x86/index.rst | 1 + Documentation/arch/x86/shstk.rst | 169 +++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) create mode 100644 Documentation/arch/x86/shstk.rst diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index c73d133fd37c..8ac64d7de4dc 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -22,6 +22,7 @@ x86-specific Documentation mtrr pat intel-hfi + shstk iommu intel_txt amd-memory-encryption diff --git a/Documentation/arch/x86/shstk.rst b/Documentation/arch/x86/shstk.rst new file mode 100644 index 000000000000..f09afa504ec0 --- /dev/null +++ b/Documentation/arch/x86/shstk.rst @@ -0,0 +1,169 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================== +Control-flow Enforcement Technology (CET) Shadow Stack +====================================================== + +CET Background +============== + +Control-flow Enforcement Technology (CET) covers several related x86 processor +features that provide protection against control flow hijacking attacks. CET +can protect both applications and the kernel. + +CET introduces shadow stack and indirect branch tracking (IBT). A shadow stack +is a secondary stack allocated from memory which cannot be directly modified by +applications. When executing a CALL instruction, the processor pushes the +return address to both the normal stack and the shadow stack. Upon +function return, the processor pops the shadow stack copy and compares it +to the normal stack copy. If the two differ, the processor raises a +control-protection fault. IBT verifies indirect CALL/JMP targets are intended +as marked by the compiler with 'ENDBR' opcodes. Not all CPU's have both Shadow +Stack and Indirect Branch Tracking. Today in the 64-bit kernel, only userspace +shadow stack and kernel IBT are supported. + +Requirements to use Shadow Stack +================================ + +To use userspace shadow stack you need HW that supports it, a kernel +configured with it and userspace libraries compiled with it. + +The kernel Kconfig option is X86_USER_SHADOW_STACK. When compiled in, shadow +stacks can be disabled at runtime with the kernel parameter: nousershstk. + +To build a user shadow stack enabled kernel, Binutils v2.29 or LLVM v6 or later +are required. + +At run time, /proc/cpuinfo shows CET features if the processor supports +CET. "user_shstk" means that userspace shadow stack is supported on the current +kernel and HW. + +Application Enabling +==================== + +An application's CET capability is marked in its ELF note and can be verified +from readelf/llvm-readelf output:: + + readelf -n | grep -a SHSTK + properties: x86 feature: SHSTK + +The kernel does not process these applications markers directly. Applications +or loaders must enable CET features using the interface described in section 4. +Typically this would be done in dynamic loader or static runtime objects, as is +the case in GLIBC. + +Enabling arch_prctl()'s +======================= + +Elf features should be enabled by the loader using the below arch_prctl's. They +are only supported in 64 bit user applications. These operate on the features +on a per-thread basis. The enablement status is inherited on clone, so if the +feature is enabled on the first thread, it will propagate to all the thread's +in an app. + +arch_prctl(ARCH_SHSTK_ENABLE, unsigned long feature) + Enable a single feature specified in 'feature'. Can only operate on + one feature at a time. + +arch_prctl(ARCH_SHSTK_DISABLE, unsigned long feature) + Disable a single feature specified in 'feature'. Can only operate on + one feature at a time. + +arch_prctl(ARCH_SHSTK_LOCK, unsigned long features) + Lock in features at their current enabled or disabled status. 'features' + is a mask of all features to lock. All bits set are processed, unset bits + are ignored. The mask is ORed with the existing value. So any feature bits + set here cannot be enabled or disabled afterwards. + +The return values are as follows. On success, return 0. On error, errno can +be:: + + -EPERM if any of the passed feature are locked. + -ENOTSUPP if the feature is not supported by the hardware or + kernel. + -EINVAL arguments (non existing feature, etc) + +The feature's bits supported are:: + + ARCH_SHSTK_SHSTK - Shadow stack + ARCH_SHSTK_WRSS - WRSS + +Currently shadow stack and WRSS are supported via this interface. WRSS +can only be enabled with shadow stack, and is automatically disabled +if shadow stack is disabled. + +Proc Status +=========== +To check if an application is actually running with shadow stack, the +user can read the /proc/$PID/status. It will report "wrss" or "shstk" +depending on what is enabled. The lines look like this:: + + x86_Thread_features: shstk wrss + x86_Thread_features_locked: shstk wrss + +Implementation of the Shadow Stack +================================== + +Shadow Stack Size +----------------- + +A task's shadow stack is allocated from memory to a fixed size of +MIN(RLIMIT_STACK, 4 GB). In other words, the shadow stack is allocated to +the maximum size of the normal stack, but capped to 4 GB. In the case +of the clone3 syscall, there is a stack size passed in and shadow stack +uses this instead of the rlimit. + +Signal +------ + +The main program and its signal handlers use the same shadow stack. Because +the shadow stack stores only return addresses, a large shadow stack covers +the condition that both the program stack and the signal alternate stack run +out. + +When a signal happens, the old pre-signal state is pushed on the stack. When +shadow stack is enabled, the shadow stack specific state is pushed onto the +shadow stack. Today this is only the old SSP (shadow stack pointer), pushed +in a special format with bit 63 set. On sigreturn this old SSP token is +verified and restored by the kernel. The kernel will also push the normal +restorer address to the shadow stack to help userspace avoid a shadow stack +violation on the sigreturn path that goes through the restorer. + +So the shadow stack signal frame format is as follows:: + + |1...old SSP| - Pointer to old pre-signal ssp in sigframe token format + (bit 63 set to 1) + | ...| - Other state may be added in the future + + +32 bit ABI signals are not supported in shadow stack processes. Linux prevents +32 bit execution while shadow stack is enabled by the allocating shadow stacks +outside of the 32 bit address space. When execution enters 32 bit mode, either +via far call or returning to userspace, a #GP is generated by the hardware +which, will be delivered to the process as a segfault. When transitioning to +userspace the register's state will be as if the userspace ip being returned to +caused the segfault. + +Fork +---- + +The shadow stack's vma has VM_SHADOW_STACK flag set; its PTEs are required +to be read-only and dirty. When a shadow stack PTE is not RO and dirty, a +shadow access triggers a page fault with the shadow stack access bit set +in the page fault error code. + +When a task forks a child, its shadow stack PTEs are copied and both the +parent's and the child's shadow stack PTEs are cleared of the dirty bit. +Upon the next shadow stack access, the resulting shadow stack page fault +is handled by page copy/re-use. + +When a pthread child is created, the kernel allocates a new shadow stack +for the new thread. New shadow stack creation behaves like mmap() with respect +to ASLR behavior. Similarly, on thread exit the thread's shadow stack is +disabled. + +Exec +---- + +On exec, shadow stack features are disabled by the kernel. At which point, +userspace can choose to re-enable, or lock them.