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bh=n5JuGTxMehujF2hW5yjYC2rYcF2MyOBRN8Ek1lm+OQ8=; b=v6vtdEYGO07DAE5iFQ66CUz422 4gRsIdrkhM465InPQ8/JnqOq0IG7KzUhaCoe3gRmSP4XJCbA1zUml/Y4VS6dAKxZZ4N/5RZjHuN87 qFAsrNfw7teoWxYTYbZCiF8pFZnjmUgiRCzzjcwDtmgtr8VAUvFeuhmF6ab90f3xCGgsog6KA9feL W5DhRN/ugE2aKKCau9+a+puGlTUVZRO+aEhD4bYP+PsCwD2qvvkUWtuFTy9VYMt8pfiQ9Y3V/60BF /hxmrNg806AS1AMQX5X5zpKy/CC56VqSPSMoXWpMaWWUUVHCgBTLtfpRRCK/7rtJ4XjW3BA93ABwT inAW3qHA==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qIxjT-00Eupy-NG; Mon, 10 Jul 2023 20:43:43 +0000 From: "Matthew Wilcox (Oracle)" To: Andrew Morton Cc: "Matthew Wilcox (Oracle)" , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Alexandre Ghiti , Mike Rapoport , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Subject: [PATCH v5 22/38] riscv: Implement the new page table range API Date: Mon, 10 Jul 2023 21:43:23 +0100 Message-Id: <20230710204339.3554919-23-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230710204339.3554919-1-willy@infradead.org> References: <20230710204339.3554919-1-willy@infradead.org> MIME-Version: 1.0 X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: 982C9140005 X-Stat-Signature: rhw3g9sq7tnbsjycn4xtxap1x8cre9km X-Rspam-User: X-HE-Tag: 1689021826-560492 X-HE-Meta: U2FsdGVkX1/eXdYduRDtQDk4FqMQBb8QxcE9GES3omr7p0yRJ3GsXdP/wC/eJON8DRbYRlkPChJXVXn4RG3s/z+4XuMgbX2+PkQp2vFL4SoibB/fw2Rf1JH2/DvviV69WdTIJ/aE9zrFYTbpRflq5iheBPLQRv36LiOFn+o4w5rm1x7+ihZF3Tq0c2Nez3ybT1D+kcwZ6EQnUl+2M2vuDJYC6wMeYXJRCfeGs701Ngy6MUEZ8ecoMAGlkgiH5GjPng5UyyBKIVOeM4iD0YVSUhpfewbTTjg3cd8wZiwx21TC3uc7TpLDtsYlb6JcSV+PqEX4sKI+9AufWczWfx/RnrdWMTxgXyEU+llFYcahpQw+wBYPD9Xqf4tf2Qpwb4+IHkR90uXEAiPfkzzGM8pN4ESk9z6SpZaCcsLyOFjR3EsquCcwalOh6nm1qi5/wkGINGY4Ko5cHmqMT729SwVi733kYWvNJBJ0X9mRLzcjVfb/jFJkLKYCWk4Rg29GzUDFiQgi+4zF7L4w3n5zZ4XR/rrAz6B1s7iWqfe1LGl75IDKXJotmBydG4K45Cbsz9aMEzmHC9V+Ow0VTz2ZhwbkDTcsmV0xI7qtzZFeGWBl/COPbC8J8/PvKzbgU8Gn8046gIiQWDGtDYk3UQ1VKrGmBhHvqvYO1MoCuo5NL7VBe0eM7B+S3QCt9JG1CHIqU7Qs6k/MVkON+L6DMGV9yX5IU3cntZEJH3nAmaWSq9e+rdc5dCZJCNMlkrHWabOLCddBe4Bbv6K+Jk4lGLe9Y3JKzskOynkXXz+XuNIwajBc/czFYb/E/8b65q5CaWoppmeDy93Icuhg4rfAPWP3qXLmBQ4mf3fIKzRnBAP6SdT8W6Duek+5gHPoi/q9/2rBHp9loiy8u14X1YAIriAENfxkd9c+pf1S9+N/GHabHmeI+Tx8J/3pqnu1MUbya5Cg27kyM0C5RWSI0JXqjP5KnKn Kv+Lotwx WSa2j2+nViODoxh0udUd7i02i8NIFdxAVg+B6bTUwF+1TenQEYN43Vnlg2gwIKfnGw2/ywfepvlTplvtE86cTRdA70cjLNuK3ftzown5yXR466I9wKYE3y5MVJEEoLMKiTsz5cZLH/1osivOZs0EC+lzniSE6urosC8PBlwzbWfiNREn7XFF1tgI8FPHclYyZ8SGkhZ6HOQFa/h8dwAoYBzJVmNGqfgb498lduS6PwsIlOQnrUZyHN0oS1xpcW+S63r5rD1RHxsvsWFk9dAgCQ1/qqSJJA3HgtI437ssOLzDJyN2gX+lZBFRTUF/YC2uQ2RiFUQ3tBU3ynXF4dBOI8p6IK0gW/sXtBJAjuOGtSozLjobxrJxQKQeFi/gZ1tHoOrntVrq5zy9Pgl2mOyq04uWw9D68vk8e0ailMjKznM2vCho= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). Change the PG_dcache_clean flag from being per-page to per-folio. Signed-off-by: Matthew Wilcox (Oracle) Reviewed-by: Alexandre Ghiti Acked-by: Mike Rapoport (IBM) Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Albert Ou Cc: linux-riscv@lists.infradead.org Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/cacheflush.h | 19 +++++++-------- arch/riscv/include/asm/pgtable.h | 38 +++++++++++++++++++---------- arch/riscv/mm/cacheflush.c | 13 +++------- 3 files changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..0d8c92c5dfb7 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -15,20 +15,19 @@ static inline void local_flush_icache_all(void) #define PG_dcache_clean PG_arch_1 -static inline void flush_dcache_page(struct page *page) +static inline void flush_dcache_folio(struct folio *folio) { - /* - * HugeTLB pages are always fully mapped and only head page will be - * set PG_dcache_clean (see comments in flush_icache_pte()). - */ - if (PageHuge(page)) - page = compound_head(page); - - if (test_bit(PG_dcache_clean, &page->flags)) - clear_bit(PG_dcache_clean, &page->flags); + if (test_bit(PG_dcache_clean, &folio->flags)) + clear_bit(PG_dcache_clean, &folio->flags); } +#define flush_dcache_folio flush_dcache_folio #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 +static inline void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); +} + /* * RISC-V doesn't have an instruction to flush parts of the instruction cache, * so instead we just flush the whole thing. diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 2137e36595b3..c8f897ed5fd0 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -445,8 +445,9 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) /* Commit new configuration to MMU hardware */ -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t *ptep) +static inline void update_mmu_cache_range(struct vm_fault *vmf, + struct vm_area_struct *vma, unsigned long address, + pte_t *ptep, unsigned int nr) { /* * The kernel assumes that TLBs don't cache invalid entries, but @@ -455,8 +456,11 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, * Relying on flush_tlb_fix_spurious_fault would suffice, but * the extra traps reduce performance. So, eagerly SFENCE.VMA. */ - local_flush_tlb_page(address); + while (nr--) + local_flush_tlb_page(address + nr * PAGE_SIZE); } +#define update_mmu_cache(vma, addr, ptep) \ + update_mmu_cache_range(NULL, vma, addr, ptep, 1) #define __HAVE_ARCH_UPDATE_MMU_TLB #define update_mmu_tlb update_mmu_cache @@ -487,8 +491,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) void flush_icache_pte(pte_t pte); -static inline void __set_pte_at(struct mm_struct *mm, - unsigned long addr, pte_t *ptep, pte_t pteval) +static inline void __set_pte_at(pte_t *ptep, pte_t pteval) { if (pte_present(pteval) && pte_exec(pteval)) flush_icache_pte(pteval); @@ -496,17 +499,26 @@ static inline void __set_pte_at(struct mm_struct *mm, set_pte(ptep, pteval); } -static inline void set_pte_at(struct mm_struct *mm, - unsigned long addr, pte_t *ptep, pte_t pteval) +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pteval, unsigned int nr) { - page_table_check_ptes_set(mm, addr, ptep, pteval, 1); - __set_pte_at(mm, addr, ptep, pteval); + page_table_check_ptes_set(mm, addr, ptep, pteval, nr); + + for (;;) { + __set_pte_at(ptep, pteval); + if (--nr == 0) + break; + ptep++; + addr += PAGE_SIZE; + pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; + } } +#define set_ptes set_ptes static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { - __set_pte_at(mm, addr, ptep, __pte(0)); + __set_pte_at(ptep, __pte(0)); } #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS @@ -515,7 +527,7 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma, pte_t entry, int dirty) { if (!pte_same(*ptep, entry)) - set_pte_at(vma->vm_mm, address, ptep, entry); + __set_pte_at(ptep, entry); /* * update_mmu_cache will unconditionally execute, handling both * the case that the PTE changed and the spurious fault case. @@ -688,14 +700,14 @@ static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, pmd_t pmd) { page_table_check_pmd_set(mm, addr, pmdp, pmd); - return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); + return __set_pte_at((pte_t *)pmdp, pmd_pte(pmd)); } static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, pud_t *pudp, pud_t pud) { page_table_check_pud_set(mm, addr, pudp, pud); - return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); + return __set_pte_at((pte_t *)pudp, pud_pte(pud)); } #ifdef CONFIG_PAGE_TABLE_CHECK diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fbc59b3f69f2..f1387272a551 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -82,18 +82,11 @@ void flush_icache_mm(struct mm_struct *mm, bool local) #ifdef CONFIG_MMU void flush_icache_pte(pte_t pte) { - struct page *page = pte_page(pte); + struct folio *folio = page_folio(pte_page(pte)); - /* - * HugeTLB pages are always fully mapped, so only setting head page's - * PG_dcache_clean flag is enough. - */ - if (PageHuge(page)) - page = compound_head(page); - - if (!test_bit(PG_dcache_clean, &page->flags)) { + if (!test_bit(PG_dcache_clean, &folio->flags)) { flush_icache_all(); - set_bit(PG_dcache_clean, &page->flags); + set_bit(PG_dcache_clean, &folio->flags); } } #endif /* CONFIG_MMU */