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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id 12-20020a05600c020c00b003fbfa6066acsm1750168wmi.40.2023.07.11.00.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 00:58:40 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH 4/4] riscv: Improve flush_tlb_kernel_range() Date: Tue, 11 Jul 2023 09:54:34 +0200 Message-Id: <20230711075434.10936-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230711075434.10936-1-alexghiti@rivosinc.com> References: <20230711075434.10936-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 5F64DC0013 X-Rspam-User: X-Rspamd-Server: rspam11 X-Stat-Signature: a93cwixtwwgbxhm6xkzwdnwgmc5r6yn6 X-HE-Tag: 1689062322-464103 X-HE-Meta: U2FsdGVkX19lb8Di9cmYDU4ILIYdh35eJU66+3f+6COLZPmQ07dpZOl5uEYDPUuyFTFjRkT2xtdh5RmhWpZLUTmwOoaW1hXw7n9xrZVhQ8NFFXUfT7Ir/zRf+cQdvubbhpwtGJ0ENKbfZAVGigQ3JVVt8zFfT8TlgEGYVF/J0qkBfEVwDa+AG8l5DEReT4rBVCHFCvTrc7PhwbQUwYwNcDOgHShhmdJvaRBOYUtjPKAWmYHCelppJY67bGCUSkX6BjSlaUAWSx0rpKJTusGGglBTj60cXHtOts+266hWJFsOtHhWDNDxB54ZnCHxiEckkwd9MFHYX7QkUlGcKFZ7q37CLDBfV/760gvAyGJmhrr7aKbKOguEcoA+O9O7CgNZJTt846YDzqwjcTMc4hl5Ir4vU9+L7wpCfPN2rrDTSUIXf4gmsktVX0NQUcTxkxn+WS0gnKcc5iOWpPesA3nAocjf1NVLnq01JQn9EKW1gUvYzp0EJbC+8L76Xk3uKDYPUjNbaKihmHcTuNMEjRB1Bg0ACgZkgYUJKfq6djXFxD2GyrtV0sQHNjWYCfVYuQS6Xx6P7a0rBVe9UD3uf0+khaAOGu7l/jrLvTV+R3C6MrcIk+D8gXngyxN5a8mzsjpORBNMjVo/SE7eeiRXKjMClg2cf1GUrr1vmqG5NK+CaVnSncxEugbNn06EDG8vHslvf5H+aNVhLNl4/iXtR/y2z5JdsmDnbWRwK1WhynzDn1639VuHVabAzYO/M77ErKg8m03OjyGthD3scN0iRAc+bBG5Ts/DHyJ+/68Hz1CQKbYeFieNogGRXaA7/XQIM3HOzpAv8LdrQMeeudqnrSjg6RCKrSpABcANXGiiiyfcTmUVsUSGvgHZXhzaY50y1Nv1YH4ARFhwelMBeTtUL3dYZ3Ip5XUfavbjM0RUQGDLmUB04TsFBZPS4zplXyw+SPWCC7NggsICygooOZSFQgh hUWBY5rx FsbRu0FQHHJpcwOrlLkEpyvFsyY2/1nQpu8guBDox/yUi+iSiJbfWzZPKRH/x7PznQCOAvc1EcZBaDm7xwC2mY0kyc2HnIl5RIpddsIxCx4/N0zsiuc1vq/y2TMw0jkVNqdF5oYuZZY1Rmn81tjXTsargf/P9emGizydwF392eNwRHGH9tvpgi0LKcq6PQtDkLF1QJ1ZQ7P4wci1rc6OKw8P1ukmGdwz/4bXsOjpeucIt5mlwRQyeZfZ/cxeY22asyUDBLitsw7N2ZrI3gBh+P6rykj7eRVqVWQpZbvDT4Y2hBXKPkTNXmrL4f5HqmmA65FK8BbaAQXZNZ6xt54+rCWQ2oLK2z3xspAbESi6k8gXf3LKJeLfuqU2FEtJdc7Edfo4eytoTp9aAWtPLhpUB2cYezwd9Z9pzXVVtwWz5ZtjKnRSVnf/5B67i2fYWIh7LdU9rb+2xAlin5/aDzf5A0mGBQ7mabNmgq/nPBtzOrJtGhvPYPsSryrrEXA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti --- arch/riscv/include/asm/tlbflush.h | 11 +++++----- arch/riscv/mm/tlbflush.c | 35 +++++++++++++++++++++++-------- 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index f5c4fb0ae642..7426fdcd8ec5 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +void flush_tlb_kernel_range(unsigned long start, unsigned long end); #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, local_flush_tlb_all(); } -#define flush_tlb_mm(mm) flush_tlb_all() -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() -#endif /* !CONFIG_SMP || !CONFIG_MMU */ - /* Flush a range of kernel pages */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - flush_tlb_all(); + local_flush_tlb_all(); } +#define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() +#endif /* !CONFIG_SMP || !CONFIG_MMU */ + #endif /* _ASM_RISCV_TLBFLUSH_H */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index de61ecaa218a..07cfed83bec8 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -117,18 +117,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long size, unsigned long stride) { struct flush_tlb_range_data ftd; - struct cpumask *cmask = mm_cpumask(mm); - unsigned int cpuid; + struct cpumask *cmask, full_cmask; bool broadcast; - if (cpumask_empty(cmask)) - return; + if (mm) { + unsigned int cpuid; + + cmask = mm_cpumask(mm); + if (cpumask_empty(cmask)) + return; + + cpuid = get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + } else { + cpumask_setall(&full_cmask); + cmask = &full_cmask; + broadcast = true; + } - cpuid = get_cpu(); - /* check if the tlbflush needs to be sent to other CPUs */ - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; if (static_branch_unlikely(&use_asid_allocator)) { - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0; if (broadcast) { if (riscv_use_ipi_for_rfence()) { @@ -162,7 +171,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, } } - put_cpu(); + if (mm) + put_cpu(); } void flush_tlb_mm(struct mm_struct *mm) @@ -194,6 +204,13 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, 1 << stride_shift); } + +void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + __flush_tlb_range(NULL, start, end, PAGE_SIZE); +} + #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)