From patchwork Sun Jul 16 21:51:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13314936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF34EB64DD for ; Sun, 16 Jul 2023 21:53:18 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 08A376B007B; Sun, 16 Jul 2023 17:53:18 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 037DD6B007D; Sun, 16 Jul 2023 17:53:17 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id E1B248D0001; Sun, 16 Jul 2023 17:53:17 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id CFF2F6B007B for ; Sun, 16 Jul 2023 17:53:17 -0400 (EDT) Received: from smtpin04.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id 920891201DD for ; Sun, 16 Jul 2023 21:53:17 +0000 (UTC) X-FDA: 81018826434.04.C879616 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by imf17.hostedemail.com (Postfix) with ESMTP id A37994001E for ; Sun, 16 Jul 2023 21:53:15 +0000 (UTC) Authentication-Results: imf17.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=Pw9nSbj1; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf17.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1689544395; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=/J5gml/ZvxPeYzFnar7ZRh22Rpheqf3o6tjd+YpoQ6Y=; b=wUz5btoH+2c0IvNEo2aTJEpPdJNlkYXL2jC29YQthtN2JWQOKxwteY5vXF1Dl9b7w2pR10 sh6j+uC09Ea+dTTspeCON3Y+gMEcZHbqse9+CYcUww98tqDSUuSDkII6tH8tLCY7Stcs6u Ag+PHtm001Mk2xRPT2nTZDoGsBktWs8= ARC-Authentication-Results: i=1; imf17.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=Pw9nSbj1; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf17.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1689544395; a=rsa-sha256; cv=none; b=FjGzbBeHecw1TOMnsL8TDg/YHV++8VuzR7RBn2xC1txrnGPyCjUAaS4V3xHD79Y177K62J F6JB8vd678bz65tMH/Z2zT0ezyj5Gf8IdPX82cioERswepGdP6rtxREnbWaFg1sKFck6mS QLJ5DAApB9AwwpraV+YsHnzJmQvuWGk= Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CAF5A60ECB; Sun, 16 Jul 2023 21:53:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E395DC433D9; Sun, 16 Jul 2023 21:53:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689544394; bh=NwoSrueebyEbURTt6m5toCTRYZrdX6jgyTyrkGE3+ZU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Pw9nSbj1Ol7LPGjSLs98tJZ2ACUWuX7wQQYkilyMpsfCvAB45wovv6V2mzuuIz0uF Ta9n6jqp1qhuzblLgIlKp2vP7Ul52k71KP4cJzkYbD3i+k05japnbgt35ldTDVMe/g pCIKWHuF/Gs3+Sbq8i7OIJBcVxYDVUaW8bXhdtOwtIu/RvNPXfMVM2xQPeYUYBTctJ mQSCw3zgqneH2ozN128Ws1sFq7EvVGjkPDvzbbMaYjIsqv4ny60tqx6djj4hR3OnsS uzzLsoIKqCwVNx0MqfyIh/WawOG/vY90tZPVxETP5zt14KoGdgE90OitpvwvPVacHI Jy1pwbEsiEsOw== From: Mark Brown Date: Sun, 16 Jul 2023 22:51:00 +0100 Subject: [PATCH 04/35] arm64/gcs: Document the ABI for Guarded Control Stacks MIME-Version: 1.0 Message-Id: <20230716-arm64-gcs-v1-4-bf567f93bba6@kernel.org> References: <20230716-arm64-gcs-v1-0-bf567f93bba6@kernel.org> In-Reply-To: <20230716-arm64-gcs-v1-0-bf567f93bba6@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-099c9 X-Developer-Signature: v=1; a=openpgp-sha256; l=9701; i=broonie@kernel.org; h=from:subject:message-id; bh=NwoSrueebyEbURTt6m5toCTRYZrdX6jgyTyrkGE3+ZU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBktGaSuKIlLy3iIp8ZfqhQgcwhUn68HYcvTih8Ur8s CrVsnHSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZLRmkgAKCRAk1otyXVSH0D6eB/ 4uDk8zcAj9uslFWZsdWHaI/spnjukr91kjXqhcXwjOBoy5ks8ezHxFq85f88Hjo+ZzlfaOHQE2LM94 EdjqhTEnKU3Zns91S6GxAnVkHmU5COOoKkLCMVdHPz8EOMVX8UUKEBlbUvUuHQ3prpAJ0w/p5HzYmO 7iau5RKuKAeBNB4XVnY4Fb3J4Zo7pnI/uo/Na4onG/qOcXWuVM495JlGub1WFWFG8+D8CrbvaJIWAt c7bDhBK4PsLm1x5xQy7q+7KiJfkT3BHkLt2C/EvsRtVHpASq+5RO1a2n/obgaPyUlIAdDgZSmjpS/D tzXAJHxZPdPsm4kzNDCPAKNY4nW5gv X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: A37994001E X-Stat-Signature: us533e6kzd6ztuh3f8gty7pg6kudgk5n X-HE-Tag: 1689544395-290876 X-HE-Meta: U2FsdGVkX1/5oeNP/M8nKTOQ9EiLtQXI2MDFn8sekrIe9DjN1m27d5vXrSBQFycvJ9HnucFrKkpXaGlzKZ2ulNJxXq7i216LwVSe+UnPMf30HTo+umBtGn1Qn19L8cvqDCRnBShmWybL7wzL63WQdmVptTwV7aHlBsW3SYaVL8YMfUbSE4lSpTI2OCGJW0gpSHQqcItRhg6KcX4wWLGuHzmIE/9+Z9Qd2s+/aec+s1ETr06AF+Lb2WEYPpAvfctwY92NnWOBHbJBtjK1c9AxSSToLSbDtjEvgISvKlp06g1UFUKZqiqHaSOihfIEed1OLZKrB9IF9adWATXfe67BIFa6GjpRAM0ZVxHlwOXdc1QXfQc0283CiYZe5H3B5AJSxGLy0YF6ZfXd06JNNp1wHt2Wf7KhRom1sqNNIER4knkhv+pDQswWWfiz8bsii1/MzGBE5LeYHL5NUuMU/1CAC6RVgrxTmsZc4lVkBK80rTmrvtqxdLryVbjCN/y1HFAp+2uLEcV3lyBlhRGq5SSMdV/+3IHWh8lIbwxraE8ipLpTBkG/k0/fX6tDocZukzd0hvpYgXZQXEhMfQkgBNPb/tuwN32dXowGAsxvy5S3VoOBMCDR2Bwa7ve0z9xRb4m27f7d9/t9SVa85L53XP9xatcCgQ/HxYFA3LNyhq43PvXYFyAM85oevc30mP5EEkdmWwAyLGTFm1NNZ6OptltWg5Nr6bTPjmtjVknPkrc2g1GB4clhicusyBLdy9qLfVRVGMdiXxI8cOOq+CHgnajqOXYEZ/2kI54XHp64tfmEE4LAbOVV+oAAGC8sQAdheSxyPPGo7ab8fmxjJ8hQLMm95yGXoC2Unt4c9nGFEyQW3Jys3gxbh15C/Z+ErOSHTZqH5BOMj+5F3F7EXdApS4CdR740y37ds/XiJjZrhsDFj+2MO9Myavo3rJvjdKJ/LE33I+HUcwHfzW1pPwidSLe FURtefNO WFvrPNT0NO3z10KDYemJ0fIxfcPJ+F5HSX8JAOfcaqR02XpagqblCrOj9s8wTQHqkIRNCkr4a/X2y7OBaOV/uiMT75F326qqywGUc16zfrHzJB4YFwtRDQ/EGEWie67iRHXSlDsvCo2/48ie5vL3lUinpzNLR6tJMYO2j0oNSzVs//7DdvC+8G8i6FBDPuKCU36EItVg8f5hwxl6a2Ag33V70WbYH3jaQGKAtndxEqExw+GR/NSWjFlEQJE6ZWaj+eoNcOKUVLISKo5b+vef9HuPuyLIlh/TKXrK0/vHsEiY32fx+3MFdJH4ko6XZFmJAiGMLEhG/qW8Z6WmaFa8szViTICs34U8wM34U5dF7Q8dfrWPFH6IBs1LQVaSRLl87hrfFG0PZ6pgBM6zZ3saxhblTp+a+3ZKK7cup6MAgchhgZUk= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add some documentation of the userspace ABI for Guarded Control Stacks. Signed-off-by: Mark Brown --- Documentation/arch/arm64/gcs.rst | 216 +++++++++++++++++++++++++++++++++++++ Documentation/arch/arm64/index.rst | 1 + 2 files changed, 217 insertions(+) diff --git a/Documentation/arch/arm64/gcs.rst b/Documentation/arch/arm64/gcs.rst new file mode 100644 index 000000000000..27ba72d27952 --- /dev/null +++ b/Documentation/arch/arm64/gcs.rst @@ -0,0 +1,216 @@ +=============================================== +Guarded Control Stack support for AArch64 Linux +=============================================== + +This document outlines briefly the interface provided to userspace by Linux in +order to support use of the ARM Guarded Control Stack (GCS) feature. + +This is an outline of the most important features and issues only and not +intended to be exhaustive. + + + +1. General +----------- + +* GCS is an architecture feature intended to provide greater protection + against return oriented programming (ROP) attacks and to simplify the + implementation of features that need to collect stack traces such as + profiling. + +* When GCS is enabled a separate guarded control stack is maintained by the + PE which is writeable only through specific GCS operations. This + stores the call stack only, when a procedure call instruction is + performed the current PC is pushed onto the GCS and on RET the + address in the LR is verified against that on the top of the GCS. + +* When active current GCS pointer is stored in the system register + GCSPR_EL0. This is readable by userspace but can only be updated + via specific GCS instructions. + +* The architecture provides instructions for switching between guarded + control stacks with checks to ensure that the new stack is a valid + target for switching. + +* The functionality of GCS is similar to that provided by the x86 Shadow + Stack feature, due to sharing of userspace interfaces the ABI refers to + shadow stacks rather than GCS. + +* Support for GCS is reported to userspace via HWCAP2_GCS in the aux vector + AT_HWCAP2 entry. + +* GCS is enabled per thread. While there is support for disabling GCS + at runtime this should be done with great care. + +* GCS memory access faults are reported as normal memory access faults. + +* GCS specific errors (those reported with EC 0x2d) will be reported as + SIGSEGV with a si_code of SEGV_CPERR (control protection error). + +* GCS is supported only for AArch64. + +* On systems where GCS is supported GCSPR_EL0 is always readable by EL0 + regardless of the GCS configuration for the thread. + +* The architecture supports enabling GCS without verifying that return values + in LR match those in the GCS, the LR will be ignored. This is not supported + by Linux. + +* EL0 GCS entries with bit 63 set are reserved for use, one such use is defined + below for signals and should be ignored when parsing the stack if not + understood. + + +2. Enabling and disabling Guarded Control Stacks +------------------------------------------------- + +* GCS is enabled and disabled for a thread via the PR_SET_SHADOW_STACK_STATUS + prctl(), this takes a single flags argument specifying which GCS features + should be used. + +* When set PR_SHADOW_STACK_ENABLE flag allocates a Guarded Control Stack for + and enables GCS for the thread, enabling the functionality controlled by + GCSPRE0_EL1.{nTR, RVCHKEN, PCRSEL}. + +* When set the PR_SHADOW_STACK_PUSH flag enables the functionality controlled + by GCSCRE0_EL1.PUSHMEn, allowing explicit GCS push and pops. + +* When set the PR_SHADOW_STACK_WRITE flag enables the functionality controlled + by GCSCRE0_EL1.STREn, allowing explicit stores to the Guarded Control Stack. + +* When set the PR_SHADOW_STACK_LOCK flag prevents any further configuration of + the GCS settings for the thread, further attempts to configure GCS will + return -EBUSY. + +* Any unknown flags will cause PR_SET_SHADOW_STACK_STATUS to return -EINVAL. + +* PR_SET_SHADOW_STACK_STATUS affects only the thread the called it, any + other running threads will be unaffected. + +* New threads inherit the GCS configuration of the thread that created them. + +* GCS is disabled on exec(). + +* The current GCS configuration for a thread may be read with the + PR_GET_SHADOW_STACK_STATUS prctl(), this returns the same flags that + are passed to PR_SET_SHADOW_STACK_STATUS. + +* If GCS is disabled for a thread after having previously been enabled then + the stack will remain allocated for the lifetime of the thread. At present + any attempt to reenable GCS for the thread will be rejected, this may be + revisited in future. + +* It should be noted that since enabling GCS will result in GCS becoming + active immediately it is not normally possible to return from the function + that invoked the prctl() that enabled GCS. It is expected that the normal + usage will be that GCS is enabled very early in execution of a program. + + + +3. Allocation of Guarded Control Stacks +---------------------------------------- + +* When GCS is enabled for a thread a new Guarded Control Stack will be + allocated for it of size RLIMIT_STACK / 2 or 2 gigabytes, whichever is + smaller. + +* When a new thread is created by a thread which has GCS enabled then a + new Guarded Control Stack will be allocated for the new thread with + half the size of the standard stack. + +* When a stack is allocated by enabling GCS or during thread creation then + the top 8 bytes of the stack will be initialised to 0 and GCSPR_EL0 will + be set to point to the address of this 0 value, this can be used to + detect the top of the stack. + +* Additional Guarded Control Stacks can be allocated using the + map_shadow_stack() system call. + +* Stacks allocated using map_shadow_stack() will have the top 8 bytes + set to 0 and the 8 bytes below that initialised with an architecturally + valid GCS cap value, this allows switching to these stacks using the + stack switch instructions provided by the architecture. + +* When GCS is disabled for a thread the Guarded Control Stack initially + allocated for that thread will be freed. Note carefully that if the + stack has been switched this may not be the stack currently in use by + the thread. + + +4. Signal handling +-------------------- + +* A new signal frame record gcs_context encodes the current GCS mode and + pointer for the interrupted context on signal delivery. This will always + be present on systems that support GCS. + +* The record contains a flag field which reports the current GCS configuration + for the interrupted context as PR_GET_SHADOW_STACK_STATUS would. + +* The signal handler is run with the same GCS configuration as the interrupted + context. + +* When GCS is enabled for the interrupted thread a signal handling specific + GCS cap token will be written to the GCS, this is an architectural GCS cap + token with bit 63 set. The GCSPR_EL0 reported in the signal frame will + point to this cap token. + +* The signal handler will use the same GCS as the interrupted context. + +* When GCS is enabled on signal entry a frame with the address of the signal + return handler will be pushed onto the GCS, allowing return from the signal + handler via RET as normal. This will not be reported in the gcs_context in + the signal frame. + + +5. Signal return +----------------- + +When returning from a signal handler: + +* If there is a gcs_context record in the signal frame then the GCS flags + and GCSPR_EL0 will be restored from that context prior to further + validation. + +* If there is no gcs_context record in the signal frame then the GCS + configuration will be unchanged. + +* If GCS is enabled on return from a signal handler then GCSPR_EL0 must + point to a valid GCS signal cap record, this will be popped from the + GCS prior to signal return. + +* If the GCS configuration is locked when returning from a signal then any + attempt to change the GCS configuration will be treated as an error. This + is true even if GCS was not enabled prior to signal entry. + +* GCS may be disabled via signal return but any attempt to enable GCS via + signal return will be rejected. + + +7. ptrace extensions +--------------------- + +* A new regset NT_ARM_GCS is defined for use with PTRACE_GETREGSET and + PTRACE_SETREGSET. + +* Due to the complexity surrounding allocation and deallocation of stakcs and + lack of practical application changes to the GCS configuration via ptrace + are not supported. + + + +8. ELF coredump extensions +--------------------------- + +* NT_ARM_GCS notes will be added to each coredump for each thread of the + dumped process. The contents will be equivalent to the data that would + have been read if a PTRACE_GETREGSET of the corresponding type were + executed for each thread when the coredump was generated. + + + +9. /proc extensions +-------------------- + +* Guarded Control Stack pages will include "ss" in their VmFlags in + /proc//smaps. diff --git a/Documentation/arch/arm64/index.rst b/Documentation/arch/arm64/index.rst index d08e924204bf..dcf3ee3eb8c0 100644 --- a/Documentation/arch/arm64/index.rst +++ b/Documentation/arch/arm64/index.rst @@ -14,6 +14,7 @@ ARM64 Architecture booting cpu-feature-registers elf_hwcaps + gcs hugetlbpage kdump legacy_instructions