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Sat, 29 Jul 2023 21:17:05 +0800 From: Yicong Yang To: , , , CC: <21cnbao@gmail.com>, Subject: [PATCH -mm] arm64: tlbflush: Add some comments for TLB batched flushing Date: Sat, 29 Jul 2023 21:14:48 +0800 Message-ID: <20230729131448.15531-1-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 02A46140027 X-Stat-Signature: iuit1nzwanoc73jrtquhfwfn7fgt8n8w X-HE-Tag: 1690636634-304668 X-HE-Meta: U2FsdGVkX1/Llbrl+a8hsoFuH+e26zzHjbmLDgp1ERErdnyVDuOwrHrF6NwkA4CIvXkLf/95qB31Eg2IevSK1lcRLCqTu4cDr9s7SkWYpHi5sDz736iHwT6IgIHrZYtYucJMkSLgFUTTixa8lyPR92bTtQkGMFfU+y2yalljS7tWzt+jvNXG2+rKqVSIFmN61IyukPEto+os6+B6OGgjWN6wFsHt+6YOAmP0c7vRxPqQWXClpwgED5tvDYdhaEWBxDIN9yE6p2ASDWvEiia+bbRUmj7FGRTf7tcHkX4QiWgvtJbL/fOA+8UFDwRDrgwWKuBgUJ4xubYzbbuyAwyF3WKmYe7b4xoBOY6PwAyCNJ/lPr69iRrfT4/gDiIE1ds5SLGj5O2Y8EbE/YAA5iufD4+SDqHE1ZIv8eSUw/ibUL6J+23YauFSeBLvcuYmEst6bRnl8HfwHrW3gDBcHBOvc2zBbruyBkWYqgsq0Iiuqpv0L6yyo3Znsu4CBNl41CAOwuAsB5fDoofnKU8YyodRqt2pybJbPuiNp+RLPnq/Ln0fUxqnYJtA3MO3+RdgT/jeFYjdJdiJWkqtap0S3Mkxs01j39j36zcJSLzFLf7H7D2Khs4ntaXnXBJrN0O09iTdJD/rft8v7+m+2tIm5FtNk3iDqNWlKpBH8ahjdeTqoN37XPoNln9L4eUCudAS9sfEMPj/YK/fyCBn60tSpf5EkKFBARF7Bx9wZReB4kbvDjJDbGjVpwhiKcP2hCbuJDWE1eBeKrzsJxzK7cPmGX00LLsbaNQD2x8Vavgj4XVrHaWl5xV3rPyQmd4ptcnoAGklC+X6EEGBpIGB5+cRQpT7uJe69f46WPjDBUNkZArBbUXISKmM40EeaZsDeEI/CPOFYBeqhmSTjOo3KUN0V9fSFprgvJUQj6re9a/9D/0r+i1QFO/whAHEfFnMYaNw8B8YIwyEniKGp+fVL3jfdBz quBL6OOi 48VmcVgwJBMoDNDaaKPfeNf5kDFKnIjUsPZjElbQW5z1MrQaDzcn/1k1hR4ntSeVJMHxbZdGBTQn4cmdBmyHyXxeNoqN0ASt60e4tXYRn9Y2R4Pi+uvV1EIbKnsUpCTsoK7iL7ZhXZR6X34FtTrfNHLbib77PhSMtl+5ibHhY4MQqq6ykHJ5R1BvFk0olOU6+7kFa+byXzhfWjzeCXpBULwwy/boY180MEsjGBcnnpO/qRGU= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Yicong Yang Add comments for arch_flush_tlb_batched_pending() and arch_tlbbatch_flush() to illustrate why only a DSB is needed. Cc: Catalin Marinas Signed-off-by: Yicong Yang Reviewed-by: Catalin Marinas Reviewed-by: Alistair Popple --- arch/arm64/include/asm/tlbflush.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 3456866c6a1d..2bad230b95b4 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b __flush_tlb_page_nosync(mm, uaddr); } +/* + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to + * synchronise all the TLBI issued by a DSB to avoid the race mentioned in + * flush_tlb_batched_pending(). + */ static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { dsb(ish); } +/* + * To support TLB batched flush for multiple pages unmapping, we only send + * the TLBI for each page in arch_tlbbatch_add_pending() and wait for the + * completion at the end in arch_tlbbatch_flush(). Since we've already issued + * TLBI for each page so only a DSB is needed to synchronise its effect on the + * other CPUs. + * + * This will save the time waiting on DSB comparing issuing a TLBI;DSB sequence + * for each page. + */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { dsb(ish);