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Tue, 1 Aug 2023 20:44:15 +0800 From: Yicong Yang To: , , , CC: <21cnbao@gmail.com>, , Subject: [PATCH v2 -mm] arm64: tlbflush: Add some comments for TLB batched flushing Date: Tue, 1 Aug 2023 20:42:03 +0800 Message-ID: <20230801124203.62164-1-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-Rspam-User: X-Stat-Signature: xqagtjuq6hibcbo614u65wht3nwkttzb X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 4A6D910000B X-HE-Tag: 1690893859-136063 X-HE-Meta: U2FsdGVkX1/+7t/icUV9teo97r9IvGofZGyGREiX1w1+c5EIB2aqAi61zLIn0I4ayoYyYcyh9KIrVTLFuLSJ8bDKhcSxAyxbGqmUoBBoMGDdb04QFrsr7fd98ek4HTsct53mJyExXHMD5rQVLzqDDB+6ON5R9dsv7CRiDnm7Mwke651ChtP3u92oma0wwLpG18fz7sIH2pr0gM9bkgWI8BIHVFztwA5rFzEQEGFQ0Y4spx/dDumW1oKFqWm8xfoWu2T87nkmv5IZyqK4cFwSh6iT/7lu+82uEUos+6WMRJ3Q1Vv3BP5xtVSluf1NUgFnKEZq/aH3Sssd3UR1QT2L7O4ceW2NWMu0bloRReYdAIi2whdpHHXQhnXKFM0jIRk3gBLHdIX6MCm642h7hQrZIHjI/l/ViUB7G/R4FSP6nO0BlzURzJLhPayXXnjLuZDJ4UFtm7oSFb2/9klZDoXaKDVaTsHHLOVtcHKohXr2UHn+cAY5HjRzqRLk0bgMyNzu5xWzOAum0f0L3kcNg5OZmj1k+XdNDut8sRAhDRvhReJ3HBA+B5Os8ZCTkIwohambp4Bh5cHG6qNdpkOwtEY5v/xJTORsQITZrf98mnDNXc50bkmMQdSBgjiH8wfI7Sbsf5dDoYWv+7T1Oyen3cJS5lCAgwm9kHDnoc2UOhGrsGGW3sYrPKHfJb9WSHTRGCE/A5ixTvoRKgOoaXD3gHXzjOBMqAnJpRVDwS8t7TjhLjprnSxySrffpbJcEUmueArl3p7NQ5xon7VKVqFW+So3mUOwEi/C3FbL2HQXj27+0QkrQcretanA7KJ74YHQZrK7wF0kifcQ3yO7qwV8bQtQUinIPjRIT++HSk+6FgnTfLUYCH/q53XM52O0tefwj5ahWYUTK2q+YpLm7vhfKNAgEDLMVht0Pc7djeRGqrDFj7FM174jma4SfkfW3Dypy4OIAnRgGOS/6kws1qbOauu nfQA2kQ1 g5Aco/v9NLvXlId+NZzz9gYBS6c4dfsShhoAwGd7Je/2+0pNMHrBEhwCQYdIafG6FsnQ7ozznQIMyjn+7bPIu0tloTMYY2nIvGkiyPIq2pwqy5rrQxEHvxG3AK0PZKcq0E6RIsEva6T9n2xPmBr1nUK8Th1/j1NikY0ri++fydafc55/QOeDeEN6hTLbXcfBdsYE+ErCeMd+u39yKGk2ZsnUVhY+5ornM/NymYhrg3IKygjE+KysJabcMjsNAO+ln8oxDhnYVp/KgmybM2ijz/wIyWBJjFujSaiDtL18xkZIS5iuZa7nYY1W3M1SGL2NFAzYmOvPKlFmngSZphE7WcyCzEMIk+1mwq+pB X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Yicong Yang Add comments for arch_flush_tlb_batched_pending() and arch_tlbbatch_flush() to illustrate why only a DSB is needed. Cc: Catalin Marinas Signed-off-by: Yicong Yang Reviewed-by: Alistair Popple Reviewed-by: Catalin Marinas --- Change since v1: - Address one comment from Catalin: s/by a DSB/with a DSB/ - Add tags from Catalin and Alistair Link: https://lore.kernel.org/all/20230729131448.15531-1-yangyicong@huawei.com/ arch/arm64/include/asm/tlbflush.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 3456866c6a1d..bd1acaf7f715 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b __flush_tlb_page_nosync(mm, uaddr); } +/* + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to + * synchronise all the TLBI issued with a DSB to avoid the race mentioned in + * flush_tlb_batched_pending(). + */ static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { dsb(ish); } +/* + * To support TLB batched flush for multiple pages unmapping, we only send + * the TLBI for each page in arch_tlbbatch_add_pending() and wait for the + * completion at the end in arch_tlbbatch_flush(). Since we've already issued + * TLBI for each page so only a DSB is needed to synchronise its effect on the + * other CPUs. + * + * This will save the time waiting on DSB comparing issuing a TLBI;DSB sequence + * for each page. + */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { dsb(ish);