From patchwork Tue Aug 22 13:56:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13360869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 816E2EE49A3 for ; Tue, 22 Aug 2023 14:05:08 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 0D0A528001C; Tue, 22 Aug 2023 10:05:05 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 07F9D280023; Tue, 22 Aug 2023 10:05:05 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id E63D028001C; Tue, 22 Aug 2023 10:05:04 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id C1118280023 for ; Tue, 22 Aug 2023 10:05:04 -0400 (EDT) Received: from smtpin19.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 9B85D1C9231 for ; Tue, 22 Aug 2023 14:05:04 +0000 (UTC) X-FDA: 81151912128.19.1FB74F6 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by imf22.hostedemail.com (Postfix) with ESMTP id 525FEC0051 for ; Tue, 22 Aug 2023 14:05:02 +0000 (UTC) Authentication-Results: imf22.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=o0b5IMQd; spf=pass (imf22.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1692713102; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=D1luWdQjCGgcA3yRUm5MGC+7IT3wPpdU5A/8hcfglQA=; b=bHp98eq4w6/ktUAcUdM7P9pVMI2WjcpzcRE6kfdM++bXKEv8zWv7UabzYeWGwQyxFurTcW h7rZBmHnB7TuuP9S37Ia4aygtq7Bd4CXfsR2oVFNC+kKxFJLAxFjwMa21iB1ghBDoY2oXi nRMBwJXQRmcpGblUmM1n4Nt7oj/JAHw= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1692713102; a=rsa-sha256; cv=none; b=7kWq83kUFfew4KdKOFt2JclBN7cCabMtKVXqHELkTzCTwLGRnLrw53J9+lZacYYgZxFYOJ SK8aYN8VUZWO9byAWXBAiWyM0kN6OdWwNvwlOG7QJzBIvj/SzRKKu5bTRhXiGn1ZywNSgs Q2ijAS1kRlfuZ6US10sjcs7eCTIC9S4= ARC-Authentication-Results: i=1; imf22.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=o0b5IMQd; spf=pass (imf22.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9CE9A65792; Tue, 22 Aug 2023 14:05:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3AC3AC433CC; Tue, 22 Aug 2023 14:04:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692713101; bh=PsDxGrHqBjHeoGwMKffcey2x+5qoqTXr2+aWdiIPZRc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=o0b5IMQd3dUh63/p0U6HFgzqQSsXr6EaLMBPhHYTYy+2FNCgyDC/KD+q6ZWQloUMN iO/jYoqeV/18RS1XlxxdlaHaP+KWeSl8LY5jVaB76t/5TaaFUT+GGqGY9h/Qw0lCHB raoGV3DyP+y65+uItmmOHlyyVy72SFwmjrQD37WVKR1sC4TylnpOsNvA++DMo+YlKy uyWb8yC3jpWQ0R0n/BHOVdM0B5d0+uoJ0TXrGpd03TyPG3GjVtY4g7vpyOK3UeNWHH CmXTF6gL60d6CeLVUOL85q4EfULJzBVm3ok6MnjdfpYmwEuvK0IuAT7klgdr5ivUKC rqJxUCaJr0XCg== From: Mark Brown Date: Tue, 22 Aug 2023 14:56:52 +0100 Subject: [PATCH v5 19/37] arm64/gcs: Context switch GCS state for EL0 MIME-Version: 1.0 Message-Id: <20230822-arm64-gcs-v5-19-9ef181dd6324@kernel.org> References: <20230822-arm64-gcs-v5-0-9ef181dd6324@kernel.org> In-Reply-To: <20230822-arm64-gcs-v5-0-9ef181dd6324@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6699; i=broonie@kernel.org; h=from:subject:message-id; bh=PsDxGrHqBjHeoGwMKffcey2x+5qoqTXr2+aWdiIPZRc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBk5L/+m1Yky0vwMmOZGFtWlDpMwXCDTvdyhjuABybm ZyqqcCmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZOS//gAKCRAk1otyXVSH0E8/B/ 0WzdKWWvXG143odlldMO5U0cu+b+O5F61x9nhkdw2YKEoxXMt2afByaZWvoHdO7XrUE7a8VDIxdZQq xe0NHRFaH903tESHXOLoAgYRDV8DqDLHbdO6L0a98CZcMPU8pYqjAgVexVQkM1XGbPqewaqY1wnIHn yXVA/zrTMRPXsmTUTnuFMzhbVHQOxUYlLTxxw6IvtgqW1Q9wnQAzRYdWmcEgGc2BYStjXljeeCEoMW fR6H1JM/CLAPnaCkfLVrqR/qIeHw/7ZDHnNuUoLKhHvMud5vNPmgTaXJClk1q5vVljlIrv+Elh2NWP LejpRwag5L2GBk3iTDLwGM5aUhC9Oo X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-Stat-Signature: gyrp8cmcfsaqxzy73srui1hyempw4wuj X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 525FEC0051 X-Rspam-User: X-HE-Tag: 1692713102-839928 X-HE-Meta: U2FsdGVkX1+sm7IaK679kZlFf6f2pAcR8TGll2rq9qdmwzX3awvJ5BBHtXj1+Imvqudh9cezZc3lkAPZxwpwKck2K5s5FwmWCBqlUXWiA5mtvvJXlgXvinn4Cwn4+j9sMUSnwWcJV3lIdPwd5H5QTWmHoYEjA+XTBEUYmqwBhEzK0FZAMr/059tY8inU6gKhSNB9Jf/SkQ4rrtrz6w87WKSnY8qW1yU7GXR6OOoMYWp+mlp9L4h/FbDR66ndAkIArq52DiUOBkctmafSy6h/IjBPDw7UGprfXHBVEVQCHMLckvKQPQER3LwI/XLVwrrltTkj6wTLZLn/lsx8MZlwk202j1aU/nhlO6zEYd8wUArgYmkEIlvHrA/844RKUoWRPBM7NnyPiY92onJV8wzT1XGN+FRmSYHKrW/QHxYKkayK+jObRnAayY4+paJSnUw8qIC3PqyJGxtFJ2bPSdV/srcp/SWJE92IO5yYCeowpS7lykaN+p8MqzK7f51LQsn+5fsucTQ3RJTTEeASJjV3QeEZ7MEYxHcF5B1dni/zz5MRrwvb9KTHoqdEU+W8+aHyeB/BM8ut8ohSgo7Pr0Tr1gUo/usyTEzb5ipjSMREpM1v7+Rh+AMAyKymDbrjv/7vYWZ/w8gt6nv31wZZUYCaFyU4Q9oev5K7cQa1CJ9p5PnXZVHwIp7O5GyzRB7mQ+bYbhy8Ibbu1xPDB3WrBT0jHR0HKNHV6sKlBY+Obj7suEOIwojlk6xGegGhZJSRRIIy0+z5/93EuJgeil/45z7eiZBhe0oUEYKBUT7hMx73dc54tabO3/0C4ayk1/v/NB9rNdsxGRHffRRFIwfsIv/p9gTLdhB3KJ06/01EcbhyHbj7DQz3Y2l6xcBMIrobpL8bCY8rJABPnEmEkrhtIg2o//d19yYBgpImBqOwtw19DhHJNMPKWmnyWSLZuaHJxLIuffSUPwK2AENNt9QJJ3o a5yThsaD NqwibJgtINHZgpkOXZD4hTb4JTJ587D8fXS8VQ6S6CV0q19RbAJPPRM5OSq2rpJXVJrY2w52GyfGls8lUUyqCKGBfvjkufDivyW/fIpb8oDq/9IcNqDqJtFDVFikPHtd4OpJOmzu92cYBkSjdGBIuyx6MncXxX5nhmYlgKz980GSolYJA6NESEj8OtbVL43D/F/vJ9VPAC6kB5Isb99t/xVC1C0HnmHHcDxjFo4zyCn7wDrc8vlM6BBF+zMbjgDCof9o9RmrVuaAhGhwqIZD69OUiQEaaMIqdkEf0h+nkr8+oA4PdMGZUeDbQdSZ0Zhr6RxaZuqIa5zNWb0HzStE+UOHVXvbTpyK3ilVML5+EeZaNwV+pdRt5PPQVys1yNN+wHRZR4S/YdDFxlm74pq02GylcUpcEIlubTghSKsWtLebnPfEka7k5WXVi+1UjNeDoeoMZzhATFbGt0XQ= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: There are two registers controlling the GCS state of EL0, GCSPR_EL0 which is the current GCS pointer and GCSCRE0_EL1 which has enable bits for the specific GCS functionality enabled for EL0. Manage these on context switch and process lifetime events, GCS is reset on exec(). Also ensure that any changes to the GCS memory are visible to other PEs and that changes from other PEs are visible on this one by issuing a GCSB DSYNC when moving to or from a thread with GCS. Since the current GCS configuration of a thread will be visible to userspace we store the configuration in the format used with userspace and provide a helper which configures the system register as needed. On systems that support GCS we always allow access to GCSPR_EL0, this facilitates reporting of GCS faults if userspace implements disabling of GCS on error - the GCS can still be discovered and examined even if GCS has been disabled. Signed-off-by: Mark Brown --- arch/arm64/include/asm/gcs.h | 24 ++++++++++++++++ arch/arm64/include/asm/processor.h | 6 ++++ arch/arm64/kernel/process.c | 56 ++++++++++++++++++++++++++++++++++++++ arch/arm64/mm/Makefile | 1 + arch/arm64/mm/gcs.c | 39 ++++++++++++++++++++++++++ 5 files changed, 126 insertions(+) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index 7c5e95218db6..04594ef59dad 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -48,4 +48,28 @@ static inline u64 gcsss2(void) return Xt; } +#ifdef CONFIG_ARM64_GCS + +static inline bool task_gcs_el0_enabled(struct task_struct *task) +{ + return current->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE; +} + +void gcs_set_el0_mode(struct task_struct *task); +void gcs_free(struct task_struct *task); +void gcs_preserve_current_state(void); + +#else + +static inline bool task_gcs_el0_enabled(struct task_struct *task) +{ + return false; +} + +static inline void gcs_set_el0_mode(struct task_struct *task) { } +static inline void gcs_free(struct task_struct *task) { } +static inline void gcs_preserve_current_state(void) { } + +#endif + #endif diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index e5bc54522e71..c28681cf9721 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -179,6 +179,12 @@ struct thread_struct { u64 sctlr_user; u64 svcr; u64 tpidr2_el0; +#ifdef CONFIG_ARM64_GCS + unsigned int gcs_el0_mode; + u64 gcspr_el0; + u64 gcs_base; + u64 gcs_size; +#endif }; static inline unsigned int thread_get_vl(struct thread_struct *thread, diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 0fcc4eb1a7ab..84bac012f744 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include @@ -271,12 +272,32 @@ static void flush_tagged_addr_state(void) clear_thread_flag(TIF_TAGGED_ADDR); } +#ifdef CONFIG_ARM64_GCS + +static void flush_gcs(void) +{ + if (!system_supports_gcs()) + return; + + gcs_free(current); + current->thread.gcs_el0_mode = 0; + write_sysreg_s(0, SYS_GCSCRE0_EL1); + write_sysreg_s(0, SYS_GCSPR_EL0); +} + +#else + +static void flush_gcs(void) { } + +#endif + void flush_thread(void) { fpsimd_flush_thread(); tls_thread_flush(); flush_ptrace_hw_breakpoint(current); flush_tagged_addr_state(); + flush_gcs(); } void arch_release_task_struct(struct task_struct *tsk) @@ -474,6 +495,40 @@ static void entry_task_switch(struct task_struct *next) __this_cpu_write(__entry_task, next); } +#ifdef CONFIG_ARM64_GCS + +void gcs_preserve_current_state(void) +{ + if (task_gcs_el0_enabled(current)) + current->thread.gcspr_el0 = read_sysreg_s(SYS_GCSPR_EL0); +} + +static void gcs_thread_switch(struct task_struct *next) +{ + if (!system_supports_gcs()) + return; + + gcs_preserve_current_state(); + + gcs_set_el0_mode(next); + write_sysreg_s(next->thread.gcspr_el0, SYS_GCSPR_EL0); + + /* + * Ensure that GCS changes are observable by/from other PEs in + * case of migration. + */ + if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next)) + gcsb_dsync(); +} + +#else + +static void gcs_thread_switch(struct task_struct *next) +{ +} + +#endif + /* * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. * Ensure access is disabled when switching to a 32bit task, ensure @@ -533,6 +588,7 @@ struct task_struct *__switch_to(struct task_struct *prev, ssbs_thread_switch(next); erratum_1418040_thread_switch(next); ptrauth_thread_switch_user(next); + gcs_thread_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile index dbd1bc95967d..4e7cb2f02999 100644 --- a/arch/arm64/mm/Makefile +++ b/arch/arm64/mm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_TRANS_TABLE) += trans_pgd.o obj-$(CONFIG_TRANS_TABLE) += trans_pgd-asm.o obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ARM64_MTE) += mteswap.o +obj-$(CONFIG_ARM64_GCS) += gcs.o KASAN_SANITIZE_physaddr.o += n obj-$(CONFIG_KASAN) += kasan_init.o diff --git a/arch/arm64/mm/gcs.c b/arch/arm64/mm/gcs.c new file mode 100644 index 000000000000..b0a67efc522b --- /dev/null +++ b/arch/arm64/mm/gcs.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +#include +#include + +/* + * Apply the GCS mode configured for the specified task to the + * hardware. + */ +void gcs_set_el0_mode(struct task_struct *task) +{ + u64 gcscre0_el1 = GCSCRE0_EL1_nTR; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE) + gcscre0_el1 |= GCSCRE0_EL1_RVCHKEN | GCSCRE0_EL1_PCRSEL; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_WRITE) + gcscre0_el1 |= GCSCRE0_EL1_STREn; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_PUSH) + gcscre0_el1 |= GCSCRE0_EL1_PUSHMEn; + + write_sysreg_s(gcscre0_el1, SYS_GCSCRE0_EL1); +} + +void gcs_free(struct task_struct *task) +{ + if (task->thread.gcs_base) + vm_munmap(task->thread.gcs_base, task->thread.gcs_size); + + task->thread.gcspr_el0 = 0; + task->thread.gcs_base = 0; + task->thread.gcs_size = 0; +}