From patchwork Mon Oct 9 12:08:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13413506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1062E95A91 for ; Mon, 9 Oct 2023 12:11:16 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 38C4B8D0060; Mon, 9 Oct 2023 08:11:16 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 33C858D0031; Mon, 9 Oct 2023 08:11:16 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 1DD9D8D0060; Mon, 9 Oct 2023 08:11:16 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 0A2738D0031 for ; Mon, 9 Oct 2023 08:11:16 -0400 (EDT) Received: from smtpin30.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id D9C86C01F1 for ; Mon, 9 Oct 2023 12:11:15 +0000 (UTC) X-FDA: 81325807710.30.8957066 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by imf22.hostedemail.com (Postfix) with ESMTP id 06EF8C0016 for ; Mon, 9 Oct 2023 12:11:13 +0000 (UTC) Authentication-Results: imf22.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=WYDMFukv; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf22.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1696853474; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=7vx8l7BIhry6HW/QiKfbIbLtUs2Mt+JNVlAs/0qPdmc=; b=UYcZcyjqj+716Qbu3atJsn5mv/yZOiPi5LX6wKl24Wi2E9fXlNICjrkQlc33d/WKE9UYJi /WQ0EiatLcgm1egHcf7tz3RXiAPYkpdXxjv+O0ldzktV0sJVYAxYzsYHliIMpfkHNoV2Pm moPzqo0Dm/D1/VeQoMCAXsOM1g3jCE0= ARC-Authentication-Results: i=1; imf22.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=WYDMFukv; dmarc=pass (policy=none) header.from=kernel.org; spf=pass (imf22.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1696853474; a=rsa-sha256; cv=none; b=sftiGvJRTbEXpThk22nUXP1GoH/T8FGSDDNS5tP5T62y8zGe96J2+hJ6iEvvbrXcJ0F6cf RK15EsvLj7V3uzmjdM2AFY1sxDZxNIJdvxRlNvm5HTtI+gD4ERRFhHtnd9wyzG1O63y4Sf GgJWh8p4HQl2fhv567xt+V3dH+bTwlA= Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1E8A661120; Mon, 9 Oct 2023 12:11:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60C4EC433C7; Mon, 9 Oct 2023 12:11:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696853472; bh=GW6tFZWZl4ksg+VfOphohAAwEsls5gepRScgQqoEh7U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WYDMFukv7T9m0gMiFkQ5un6OMwLhVJimW2LIo5ALSUynuUA3BN3iGHuIw5DmkJDzY k+BDuOFNTjKXkOt8Yd3D8zx3MpYSAk3Fest+gz0rfAv0ZnbZexhf2bjWk2+99vC9Fp ao2wUiAu+Ad79Hr2wt1jP91YbJu3+3baB9WUicAX64ukgXMe2AnsJTq4q7w48knc1O Ry1utt/HlblW2/s3d5cpVCAzqhqA0vCEc6bHGsDd6oGBoaCZzWQrIv47DUfAorw9cN rUVlGjr2ZD2fCBPjDgmYJwf4oUAHgnVanfCnz2YZen6YrwahEs7w58luv1fS7AfRwf I3afFkL1Fr2DA== From: Mark Brown Date: Mon, 09 Oct 2023 13:08:39 +0100 Subject: [PATCH v6 05/38] arm64/gcs: Document the ABI for Guarded Control Stacks MIME-Version: 1.0 Message-Id: <20231009-arm64-gcs-v6-5-78e55deaa4dd@kernel.org> References: <20231009-arm64-gcs-v6-0-78e55deaa4dd@kernel.org> In-Reply-To: <20231009-arm64-gcs-v6-0-78e55deaa4dd@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=10618; i=broonie@kernel.org; h=from:subject:message-id; bh=GW6tFZWZl4ksg+VfOphohAAwEsls5gepRScgQqoEh7U=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlI+2V+3mYikR8cFIXNlZcjKefFNtUq1uuNzWrG1qB G9wE7YWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZSPtlQAKCRAk1otyXVSH0PtVB/ 40rIeZoVm7wy/nb5awPdQQ5FvdmD0JN6HvfeTSnKlc6ggxMgjiHYH6iBxxr2A93OTNgMQjUmvd5Szr NC8w0ZWqvgvVMJxLeaiW0EALtP1mB5YlsUPKsATpJBHqO54E8lYx/sB9WNhYSA718Zqh/WkR4sIjoW izP7RXq9bX86HEQj50xhAXhrfXQDFvS7j8DbP7vAKlY2/Y8Eh8ZGuasiohkWjX0IrA1L+JYFQFDXRL 5BxEvc3WnV3+rw/s5t1bVEF7qjRJdqfRqcxg7phBJlrbh8DWnEN6V8TYEh7vwOCp1tf2+L4An2HU9W /egNrBvJiVDx7qwI+unvQ8tgxjAyqd X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-Rspam-User: X-Stat-Signature: 8rxnfa6mim1y53ujcgn3azed7on59hmu X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 06EF8C0016 X-HE-Tag: 1696853473-643163 X-HE-Meta: U2FsdGVkX1/Auo5wGqoD2/7QLNKjZuH/jQbVNaFCfjX39xiQYS/RJCPwSwNiFlHRgjpMFYanoG7PudxZ/N+79LbRvYnpLBJ+aH3PDXJW2qrPQsQkETbuP6TpowTwuSgnWAwFMeUOuOE5pz2kojnO1s+p9CTwptFNKzRA9i2TPwyPj7aes3DT15rbKGxiqMwUO5BDVGKPIhBGvQTVnDwp8+PbcqPwptSX7cwAz6bmBfh8JP1fbrpWz3g7ox8nk3jM2zvw5O+z/9tYfiHIkYxd54BF5QPl0UN7npDM2TYT6XDZuH/E5fdgBPSPrl3pBnqEj4binvuUmFwzvNvJ2XA9IoO5FXaEawAXiKZGPHnideejhCpW0PV2KuAZmKsYPGq5Gl6YkSoJ/v9xIuyRtuqts0dwruoO4QECQaJpVSHnRyz/+5RPD8A3zsOAV303saxa4htoOkpk2X3Lz4Zr/D7CIlxBnFMHlQEHLnszi1qc8GfmLS3sktfl7IJGEjrcfHefRc9qFchp9krmsxdbp5b9n+tEOv/FRPAPFJ9T81mLVlIxc7BKEQzwMgkLJos91nIggbdlKWRAdZII28XeCXLIKuJYR52hyYXn1HPFfwWfd3CchUdtGAVNVCrehoDAm/8C5G00yd2+hJJ0bOybgoWxZU4RRB1FtnP5+6RXdh5uG40J99XUOU9GCz3H8XXuAcc1MteYDsNVK92tzzrhUC5DBGown7k/dJ3BZWc+AhkYUAzSb+z6pa9mJ/vMi7ne86aupkWeEkmg6B8gCLUcbUunJRPzp8GVp6xuS+XFUBqhOjGIcjZBA/NM5Bf4q7cGvR7fkI3jhOCWgmcQzCURYGBNdhJUO8bF/FzlZw5Ie9RJTWudVuWxvp92JIl0omTLjcfTOCWRkTkzaCkUS2G/8P23CFbwZiPqI8TJ3XXw3ximtWg5XnjMIPNIfnVFayjL2mfLHZBirKxl+GLpT6e/iUN OAPFICdk NyyRfDOy5T1wOYnwHjvGOUvJlF7ux92JZVnZRDDVi7t1WktvqJYI0P2MQrLzR5zNWPwk2YsJhmPLhnXbiIM8TFnVFAT1TWgmvu/TFDWu1p8mAZ6/H9fMHAvC6a3Bq86mgukdtR4OeJfXhxNIOM6U8LyPpXH314f6xdt/GW2ktmU+5/HK4BWf9ERLlffpYg9+kYF0IwWIzY7cTDk/o9oDnHtb0GKrmxc2Qgis2Hu0I2VR/D8Hn4kpwhnoIZSp0OjHKL5dDzLKgbPPvwKdSWJFdgWaihSJcb/WzD6hC7XGCNkFJJ0BU2oO+Gr6Sw+rOkmWhFQeyniVo3+br63Y= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add some documentation of the userspace ABI for Guarded Control Stacks. Signed-off-by: Mark Brown --- Documentation/arch/arm64/gcs.rst | 233 +++++++++++++++++++++++++++++++++++++ Documentation/arch/arm64/index.rst | 1 + 2 files changed, 234 insertions(+) diff --git a/Documentation/arch/arm64/gcs.rst b/Documentation/arch/arm64/gcs.rst new file mode 100644 index 000000000000..b3bf1404013c --- /dev/null +++ b/Documentation/arch/arm64/gcs.rst @@ -0,0 +1,233 @@ +=============================================== +Guarded Control Stack support for AArch64 Linux +=============================================== + +This document outlines briefly the interface provided to userspace by Linux in +order to support use of the ARM Guarded Control Stack (GCS) feature. + +This is an outline of the most important features and issues only and not +intended to be exhaustive. + + + +1. General +----------- + +* GCS is an architecture feature intended to provide greater protection + against return oriented programming (ROP) attacks and to simplify the + implementation of features that need to collect stack traces such as + profiling. + +* When GCS is enabled a separate guarded control stack is maintained by the + PE which is writeable only through specific GCS operations. This + stores the call stack only, when a procedure call instruction is + performed the current PC is pushed onto the GCS and on RET the + address in the LR is verified against that on the top of the GCS. + +* When active current GCS pointer is stored in the system register + GCSPR_EL0. This is readable by userspace but can only be updated + via specific GCS instructions. + +* The architecture provides instructions for switching between guarded + control stacks with checks to ensure that the new stack is a valid + target for switching. + +* The functionality of GCS is similar to that provided by the x86 Shadow + Stack feature, due to sharing of userspace interfaces the ABI refers to + shadow stacks rather than GCS. + +* Support for GCS is reported to userspace via HWCAP2_GCS in the aux vector + AT_HWCAP2 entry. + +* GCS is enabled per thread. While there is support for disabling GCS + at runtime this should be done with great care. + +* GCS memory access faults are reported as normal memory access faults. + +* GCS specific errors (those reported with EC 0x2d) will be reported as + SIGSEGV with a si_code of SEGV_CPERR (control protection error). + +* GCS is supported only for AArch64. + +* On systems where GCS is supported GCSPR_EL0 is always readable by EL0 + regardless of the GCS configuration for the thread. + +* The architecture supports enabling GCS without verifying that return values + in LR match those in the GCS, the LR will be ignored. This is not supported + by Linux. + +* EL0 GCS entries with bit 63 set are reserved for use, one such use is defined + below for signals and should be ignored when parsing the stack if not + understood. + + +2. Enabling and disabling Guarded Control Stacks +------------------------------------------------- + +* GCS is enabled and disabled for a thread via the PR_SET_SHADOW_STACK_STATUS + prctl(), this takes a single flags argument specifying which GCS features + should be used. + +* When set PR_SHADOW_STACK_ENABLE flag allocates a Guarded Control Stack + and enables GCS for the thread, enabling the functionality controlled by + GCSCRE0_EL1.{nTR, RVCHKEN, PCRSEL}. + +* When set the PR_SHADOW_STACK_PUSH flag enables the functionality controlled + by GCSCRE0_EL1.PUSHMEn, allowing explicit GCS pushes. + +* When set the PR_SHADOW_STACK_WRITE flag enables the functionality controlled + by GCSCRE0_EL1.STREn, allowing explicit stores to the Guarded Control Stack. + +* Any unknown flags will cause PR_SET_SHADOW_STACK_STATUS to return -EINVAL. + +* PR_LOCK_SHADOW_STACK_STATUS is passed a bitmask of features with the same + values as used for PR_SET_SHADOW_STACK_STATUS. Any future changes to the + status of the specified GCS mode bits will be rejected. + +* PR_LOCK_SHADOW_STACK_STATUS allows any bit to be locked, this allows + userspace to prevent changes to any future features. + +* There is no support for a process to remove a lock that has been set for + it. + +* PR_SET_SHADOW_STACK_STATUS and PR_LOCK_SHADOW_STACK_STATUS affect only the + thread that called them, any other running threads will be unaffected. + +* New threads inherit the GCS configuration of the thread that created them. + +* GCS is disabled on exec(). + +* The current GCS configuration for a thread may be read with the + PR_GET_SHADOW_STACK_STATUS prctl(), this returns the same flags that + are passed to PR_SET_SHADOW_STACK_STATUS. + +* If GCS is disabled for a thread after having previously been enabled then + the stack will remain allocated for the lifetime of the thread. At present + any attempt to reenable GCS for the thread will be rejected, this may be + revisited in future. + +* It should be noted that since enabling GCS will result in GCS becoming + active immediately it is not normally possible to return from the function + that invoked the prctl() that enabled GCS. It is expected that the normal + usage will be that GCS is enabled very early in execution of a program. + + + +3. Allocation of Guarded Control Stacks +---------------------------------------- + +* When GCS is enabled for a thread a new Guarded Control Stack will be + allocated for it of size RLIMIT_STACK or 4 gigabytes, whichever is + smaller. + +* When a new thread is created by a thread which has GCS enabled then a + new Guarded Control Stack will be allocated for the new thread with + half the size of the standard stack. + +* When a stack is allocated by enabling GCS or during thread creation then + the top 8 bytes of the stack will be initialised to 0 and GCSPR_EL0 will + be set to point to the address of this 0 value, this can be used to + detect the top of the stack. + +* Additional Guarded Control Stacks can be allocated using the + map_shadow_stack() system call. + +* Stacks allocated using map_shadow_stack() can optionally have an end of + stack marker and cap placed at the top of the stack. If the flag + SHADOW_STACK_SET_TOKEN is specified a cap will be placed on the stack, + if SHADOW_STACK_SET_MARKER is not specified the cap will be the top 8 + bytes of the stack and if it is specified then the cap will be the next + 8 bytes. While specifying just SHADOW_STACK_SET_MARKER by itself is + valid since the marker is all bits 0 it has no observable effect. + +* Stacks allocated using map_shadow_stack() must have a size which is a + multiple of 8 bytes larger than 8 bytes and must be 8 bytes aligned. + +* An address can be specified to map_shadow_stack(), if one is provided then + it must be aligned to a page boundary. + +* When a thread is freed the Guarded Control Stack initially allocated for + that thread will be freed. Note carefully that if the stack has been + switched this may not be the stack currently in use by the thread. + + +4. Signal handling +-------------------- + +* A new signal frame record gcs_context encodes the current GCS mode and + pointer for the interrupted context on signal delivery. This will always + be present on systems that support GCS. + +* The record contains a flag field which reports the current GCS configuration + for the interrupted context as PR_GET_SHADOW_STACK_STATUS would. + +* The signal handler is run with the same GCS configuration as the interrupted + context. + +* When GCS is enabled for the interrupted thread a signal handling specific + GCS cap token will be written to the GCS, this is an architectural GCS cap + token with bit 63 set. The GCSPR_EL0 reported in the signal frame will + point to this cap token. + +* The signal handler will use the same GCS as the interrupted context. + +* When GCS is enabled on signal entry a frame with the address of the signal + return handler will be pushed onto the GCS, allowing return from the signal + handler via RET as normal. This will not be reported in the gcs_context in + the signal frame. + + +5. Signal return +----------------- + +When returning from a signal handler: + +* If there is a gcs_context record in the signal frame then the GCS flags + and GCSPR_EL0 will be restored from that context prior to further + validation. + +* If there is no gcs_context record in the signal frame then the GCS + configuration will be unchanged. + +* If GCS is enabled on return from a signal handler then GCSPR_EL0 must + point to a valid GCS signal cap record, this will be popped from the + GCS prior to signal return. + +* If the GCS configuration is locked when returning from a signal then any + attempt to change the GCS configuration will be treated as an error. This + is true even if GCS was not enabled prior to signal entry. + +* GCS may be disabled via signal return but any attempt to enable GCS via + signal return will be rejected. + + +6. ptrace extensions +--------------------- + +* A new regset NT_ARM_GCS is defined for use with PTRACE_GETREGSET and + PTRACE_SETREGSET. + +* Due to the complexity surrounding allocation and deallocation of stacks and + lack of practical application it is not possible to enable GCS via ptrace. + GCS may be disabled via the ptrace interface. + +* Other GCS modes may be configured via ptrace. + +* Configuration via ptrace ignores locking of GCS mode bits. + + +7. ELF coredump extensions +--------------------------- + +* NT_ARM_GCS notes will be added to each coredump for each thread of the + dumped process. The contents will be equivalent to the data that would + have been read if a PTRACE_GETREGSET of the corresponding type were + executed for each thread when the coredump was generated. + + + +8. /proc extensions +-------------------- + +* Guarded Control Stack pages will include "ss" in their VmFlags in + /proc//smaps. diff --git a/Documentation/arch/arm64/index.rst b/Documentation/arch/arm64/index.rst index d08e924204bf..dcf3ee3eb8c0 100644 --- a/Documentation/arch/arm64/index.rst +++ b/Documentation/arch/arm64/index.rst @@ -14,6 +14,7 @@ ARM64 Architecture booting cpu-feature-registers elf_hwcaps + gcs hugetlbpage kdump legacy_instructions