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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2023 13:43:35.7201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 122ef2e9-87d3-4050-0962-08dbce4de54c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5861 X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 5F15140028 X-Stat-Signature: rrafapu1fhnh7oqfa3wbizw71p1ubnfk X-HE-Tag: 1697463821-505195 X-HE-Meta: U2FsdGVkX1/sX+bE8HmVLKFMaqvhCz7P6DTQrT/24t6M6TUUHib7NJCNrsHnbI0HfIlNSQVFAtgB4ACFYuzfFZ70yal04hx8SnUbFfkuzO6vSNusshrmbblKZhclxm+KoAIb6gIplyI4KpXMcOA4EbL6SDLdtDWlYxuY7RP/bExGRR5E6F/xFMB7mGv5Y4YB1H7V7jxR3gwIvMJAPSj2TfxG852ZTYOsnSdJbBDbCC294IWp0q8hy0Wm071VFwgNjbQCxgB77FFfXdSqNt5cUtRSYCPxUGoCE1+oT6WLHUY1cO8fqzKDSiHONW2ggMJptNPnwv/lyNrDN9oLpT+pC9IXXvnRRi741kmcjFfIqjJtm0BcjvyhVkXFfvTeHSASdYOC2cYb7kG75ORoTT80kpcxhmP1lFSwDj9Eh1mRmCoRTWkZEHoQBZKY5Y1Nzrhq4NLclxQCulFhXEm6gQbyTDw/rJyuvSCS0fzVm0QY0eks2k2+YJNPcm0p7Edl84smLSXzCmEXAoz6OGtM8GOzSsVSQ0M70bRjPjBdWKkBVQdJnTSGhemXcCUc7/crGeG5PPUZVehYFSic0e0JZ6AxAOjdyR0/IY+daqnnSh4RdG7shIJTCJIVJstZyjV/Fw9BKkdhCYGknMnEwc22CEa2/3valtTkiZN3UaNGvVYoqgYEXWy4ZNIjs+u2oqsgN8rW058CBkQEGwRYj3sxaTDF0FZpo+rqhT9w7G78vHKyPLVTF2TcYbzctIeE0XQZy2mAktm0Wl4u+eZQSbKuTo24/0GtXdFhe0xngbIK/WYTS5Dm7DLVukNATD9p+qOz/Qg5RCd5Jh4wfS64uaRr3IBOAxpLYDIEwyil6MUpIo9gg2q9+EuveiqyjCN1ONJQbOKTa+DvvCm7G7zz6pvMjSokvVbX+VOzb5kseNbKheBOVpMKrcyuRh2oj1N6Fg5xRtqKSpbBI7ffHEt6STlsSab OLl8AZRj NPFAgY5EiLb3nQopNAW0Qovmp4H5rhkwK2JKnvQryHvrVu1nWIDzm5vSPZOXptwGT4oUVEDvQ/EXmyLtiuWIpTEMBo8vosE2r30Hkkm7klWVSeOsDghWFLmO0gUYRYmKyQgzIKRAsvDyYXYxN6wP72FggeqJzYHgEeA+xFLJs8xU/JdAwQ+UvvewvPqK71OJdACPLbWJz2PCzA2Qd8CtgH4uZms3tSiZwyIcqbsqmPTv8B50xa00a0P2DSZNYFQ6/GAmmTiseKpanPZPlO00RjnHTGhJOF5FJiJRVWoagglQzVh/L9xz54pTiQzHJHAfl4Zq7zVZQkproZD/HBbb/gwyfVap4jGcCu7Aj3x+Vw3Rd+XdrxD3dxOR8LLoqfq3p5SH4 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: When intercepts are enabled for MSR_IA32_XSS, the host will swap in/out the guest-defined values while context-switching to/from guest mode. However, in the case of SEV-ES, vcpu->arch.guest_state_protected is set, so the guest-defined value is effectively ignored when switching to guest mode with the understanding that the VMSA will handle swapping in/out this register state. However, SVM is still configured to intercept these accesses for SEV-ES guests, so the values in the initial MSR_IA32_XSS are effectively read-only, and a guest will experience undefined behavior if it actually tries to write to this MSR. Fortunately, only CET/shadowstack makes use of this register on SEV-ES-capable systems currently, which isn't yet widely used, but this may become more of an issue in the future. Additionally, enabling intercepts of MSR_IA32_XSS results in #VC exceptions in the guest in certain paths that can lead to unexpected #VC nesting levels. One example is SEV-SNP guests when handling #VC exceptions for CPUID instructions involving leaf 0xD, subleaf 0x1, since they will access MSR_IA32_XSS as part of servicing the CPUID #VC, then generate another #VC when accessing MSR_IA32_XSS, which can lead to guest crashes if an NMI occurs at that point in time. Running perf on a guest while it is issuing such a sequence is one example where these can be problematic. Address this by disabling intercepts of MSR_IA32_XSS for SEV-ES guests if the host/guest configuration allows it. If the host/guest configuration doesn't allow for MSR_IA32_XSS, leave it intercepted so that it can be caught by the existing checks in kvm_{set,get}_msr_common() if the guest still attempts to access it. Fixes: 376c6d285017 ("KVM: SVM: Provide support for SEV-ES vCPU creation/loading") Cc: Alexey Kardashevskiy Suggested-by: Tom Lendacky Signed-off-by: Michael Roth Reported-by: Michael Roth Signed-off-by: Paolo Bonzini --- arch/x86/kvm/svm/sev.c | 19 +++++++++++++++++++ arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 4900c078045a..6ee925d66648 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2972,6 +2972,25 @@ static void sev_es_vcpu_after_set_cpuid(struct vcpu_svm *svm) set_msr_interception(vcpu, svm->msrpm, MSR_TSC_AUX, v_tsc_aux, v_tsc_aux); } + + /* + * For SEV-ES, accesses to MSR_IA32_XSS should not be intercepted if + * the host/guest supports its use. + * + * guest_can_use() checks a number of requirements on the host/guest to + * ensure that MSR_IA32_XSS is available, but it might report true even + * if X86_FEATURE_XSAVES isn't configured in the guest to ensure host + * MSR_IA32_XSS is always properly restored. For SEV-ES, it is better + * to further check that the guest CPUID actually supports + * X86_FEATURE_XSAVES so that accesses to MSR_IA32_XSS by misbehaved + * guests will still get intercepted and caught in the normal + * kvm_emulate_rdmsr()/kvm_emulated_wrmsr() paths. + */ + if (guest_can_use(vcpu, X86_FEATURE_XSAVES) && + guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_XSS, 1, 1); + else + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_XSS, 0, 0); } void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index aef1ddf0b705..1e7fb1ea45f7 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -103,6 +103,7 @@ static const struct svm_direct_access_msrs { { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, { .index = MSR_IA32_LASTINTFROMIP, .always = false }, { .index = MSR_IA32_LASTINTTOIP, .always = false }, + { .index = MSR_IA32_XSS, .always = false }, { .index = MSR_EFER, .always = false }, { .index = MSR_IA32_CR_PAT, .always = false }, { .index = MSR_AMD64_SEV_ES_GHCB, .always = true }, diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index be67ab7fdd10..c409f934c377 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -30,7 +30,7 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 46 +#define MAX_DIRECT_ACCESS_MSRS 47 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled;