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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2023 13:48:18.3689 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5ef2022-c8c3-4c22-d16c-08dbce4e8dc4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4275 X-Rspamd-Queue-Id: D91112000C X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: wsc4wdg5htymohx7rdwz9957x3yyao1q X-HE-Tag: 1697464101-351329 X-HE-Meta: U2FsdGVkX1+ldMR3M342y37AEoAOaaorPEjkOerxKrU+eFKzfAOm+bdoSdQnQFVHBI6Oz/Kvp55mS6yn38nvIeg7837Cenz9GWE7dgIVnSluOwOa9kki6QeA3PIgDwoGttj12rF2wpQQ2soattXwNnyE0JNBcxjcTKeENx9R3LUMXlOLL7hd3yFZbrIJ0bEjJDEanEVIYYusSQrbhSIE6ONMA8dYW7LqBtaD/Mni7VqfZazH/3EXUJWxYOU16Y+q121VcvSRhyPFGlVvAhnRHsw8OzVIYg0W4SgTdG0Z7da5xo9CEaRc6fhR4BxA5W3P8u1QjtnUWgjApdtuIcKkIoL813oQog1WhY9vDfjj4xavCp0GvkYiHz4VoClari0S/yhQq+c9iLTJBXAQrJjTBipinQytNZFU/GR4ULGcN0W/Qq1fOC7RZkfkIE42ilyviiJafoBCqoluSYMEb+WxqQD7DFJg3r8HhDAbw2USqG6p5yI1/vNHnJ/AIx3Hg3EzSG6z+2J9HQXkAETz8SGDLldfc42UJ/0cHkcYaxMIUWhSlQ41lsOsAHVRJQN9mYuNAtnNi7jz47LGdeJXXadMEHld6T+crif9q9rghIhUYSrOEpKKaZ4zfxT5lk2MBld32Y5dMcyvP6ktdxM3KSKzjGRNRKXBgIYBUkmeFO5tbrJCjJWCyAHVQCoHTgJOWw+dj0EH8w+DJo7Ohx8pXsxdRrJtUqWokkMtDD52hxdmZK7pUeZ8uIrhpuOLwCeb9cARyXKpL7hxMSAv1iEYTmJ047y6tRhDQpjmzeqVBXhuQlTO7+nwzqIcEQO2nyi5PeYEZ5F6O5MGpMFaDSTLF2n4WDz3+Qo03uYPDqo7S8NKyuXbfqdDqf3+3Iaq//Lni9BGvp0FAFD2eeuVpYyl878yx9I6F3KZjc3Dv/UACzH5L9BINcbZfNxSC7SyKRcCiNbUeREB4ARPmAP5rAAvCSu lVxrjf2e coVq7BD6ShN/41F93BRQT0xWd01sWPfsvQFIAZbJXlOkLCxCc7QT/+TH8DtgCOuhXPz54yYyswjqTF9fsC61G2eGuu2SC9CkJWJzQNvzfJ1/x9RKNRw5+fTX3FaCMflB8rJdqu7icr0XZTgoy9NDOFxrFlu3Cv4u5UVm3T3+X3y23NWnp5A0c9lAG3eIme0RrQ8mJGNqx3jYgN/5I6NaME+7UQflrB95dSV0AdpVBoXYDxVOhuN32GvdkMJpoS8U6L79o8DrSUwdncvviG/10sEPEREPjt5D1yACTvruQD8GmjFtLW0i6OocOdJwL7ki6Nbo+Ht3EtmMUcQmAFZpigY7MOTucAYMjwUlJQ94aGweZGfQy5FBr+ZtjSw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Brijesh Singh Add CPU feature detection for Secure Encrypted Virtualization with Secure Nested Paging. This feature adds a strong memory integrity protection to help prevent malicious hypervisor-based attacks like data replay, memory re-mapping, and more. Signed-off-by: Brijesh Singh Signed-off-by: Jarkko Sakkinen Signed-off-by: Ashish Kalra Signed-off-by: Michael Roth --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 5 +++-- tools/arch/x86/include/asm/cpufeatures.h | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 58cb9495e40f..1640cedd77f1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -437,6 +437,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* AMD SEV-ES full debug state swap support */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index dd8379d84445..14ee7f750cc7 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -630,8 +630,8 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) * SME feature (set in scattered.c). * If the kernel has not enabled SME via any means then * don't advertise the SME feature. - * For SEV: If BIOS has not enabled SEV then don't advertise the - * SEV and SEV_ES feature (set in scattered.c). + * For SEV: If BIOS has not enabled SEV then don't advertise SEV and + * any additional functionality based on it. * * In all cases, since support for SME and SEV requires long mode, * don't advertise the feature under CONFIG_X86_32. @@ -666,6 +666,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) clear_sev: setup_clear_cpu_cap(X86_FEATURE_SEV); setup_clear_cpu_cap(X86_FEATURE_SEV_ES); + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); } } diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 798e60b5454b..669f45eefa0c 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -432,6 +432,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* AMD SEV-ES full debug state swap support */