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Fri, 27 Oct 2023 11:09:19 -0700 (PDT) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com, broonie@kernel.org, catalin.marinas@arm.com, dave.hansen@linux.intel.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, James Morse , Suzuki K Poulose , Zenghui Yu Subject: [PATCH v2 07/24] arm64: enable the Permission Overlay Extension for EL0 Date: Fri, 27 Oct 2023 19:08:33 +0100 Message-Id: <20231027180850.1068089-8-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231027180850.1068089-1-joey.gouly@arm.com> References: <20231027180850.1068089-1-joey.gouly@arm.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 4F3891A000B X-Rspam-User: X-Rspamd-Server: rspam11 X-Stat-Signature: bncrzrnq6hpkeay1i1tnwrqtbuk8o345 X-HE-Tag: 1698430162-681383 X-HE-Meta: U2FsdGVkX1+JSAElq9/CFURoOVeDLYlPC9TGHJrBTLMpFlWBlU28E7eP/sh8vK79IEnOK+QyPkUD3pV9NDeDeH4CCkfphX3T5hERCh03ZDCezb1ofI56ItTkJkPNRvAtEVnUcQjiPnlLh3OmXXmBC5d8s0xnhP/7dnqujMBeTx+ixGbMUOCrYvWsJuOjgOagE8uzGzdjMwIdP8ZNUhbmXA4v9S8YJ4H6/KUaU1pa32rzsHwr7oWPcZuTEnzSX11BhuyTTbOTpYfiQj7XYZMSCeh4uFyl2w0zh8of2XoIQDy0Ku90TQNW3aBuvQqsPvF+WYZMg06epKVWqGnm+r2+GTUp8kvCpNpvABNI3xGe/Foaa08qVpMxkwq9OS9SXTig+eu3g15zhnnQUSZKoU/cjS8bWrwj1hm6/pcO2VyB0jrQE6J+4ZrAWWVj5o5BVK/r2qIhgUWMyayLXfC0nqiwhvC2srniwwZ1ycmFQgKPIRLINyFmpCtHkP0pTP89kZGariVrtMnx950dcC/Qu9VRnnbspIX6c0ksgPnCnZjqZuYMUYQbh+StcsCeiaHS7d2NV3kkSWAw9EIPuasLbf6xQZ/O1pwRc4qYRDeVx8tP+C7sW/w7YShu0olfac2Vvr/yXhVkAm71ubm+QxvD0ER5elJwU9iyQbx8VDdhL/7wY0zgzRgKz9VM+9qO6wwW7dCE30kWDwud3+IrXfzufrK5HMKyfhsrOkAgR8phqY2kruT16OsD9mctBeeBWsgxDtV2WeAfmsU9D7WCUQsiXklxLgOFLKaeUKteJJ4Dj+WT0QdNWFVM8RvlKRWHXGTMOpqEdRV28qek4VHRI0UeK1e3kznyWb0E4qLPi7P3rWPudtz12tbG+V053I1F0n7T1iytuam7FMJOXDxpEDNk2qu/oaJ1gQw32JEojG1S5r7TiTc4gz+fsCLlDaTz62lf1TUB0NckGjNRrcQsMcHwHWp iWGKybOC p24vTLSKyqCjINdbX3iFheDid5XMHrp1JluJbFH1ofHpKuOq8CT24U5DFCUtdIY4YaA0ntJ9JA+bweurZkQ42nfKmd0A0Xs7C64TLIhTVETmoU8R1Tf7bBKRodos7pbBs2olO4FXcSZwfYXBvktdAEs8uF8quMmJAKP98vRSNmbywevKoaRevnkd6OvtJYKxHTkfs9la+QfjMR1jTiFI4JOgQPf2Lu8dKYL2R X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to check if the CPU supports the feature. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon --- Documentation/arch/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 20 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 76ff9d7398fd..85f6e9babc7f 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -308,6 +308,9 @@ HWCAP2_MOPS HWCAP2_HBC Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001. +HWCAP2_POE + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 521267478d18..196f21b7d11b 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -139,6 +139,7 @@ #define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) #define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS) #define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) +#define KERNEL_HWCAP_POE __khwcap2_feature(POE) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 53026f45a509..8809ff35d6e4 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -104,5 +104,6 @@ #define HWCAP2_SME_F16F16 (1UL << 42) #define HWCAP2_MOPS (1UL << 43) #define HWCAP2_HBC (1UL << 44) +#define HWCAP2_POE (1UL << 46) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f1c1f348a31d..c79f43dfb2be 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -400,6 +400,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), + FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), ARM64_FTR_END, @@ -2220,6 +2222,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); } +#ifdef CONFIG_ARM64_POE +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); +} +#endif + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2725,6 +2735,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_HAS_S1POE, .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_poe, ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif @@ -2874,6 +2885,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), #endif /* CONFIG_ARM64_SME */ +#ifdef CONFIG_ARM64_POE + HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), +#endif {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 98fda8500535..5b44e8ab9ab8 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -127,6 +127,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_F16F16] = "smef16f16", [KERNEL_HWCAP_MOPS] = "mops", [KERNEL_HWCAP_HBC] = "hbc", + [KERNEL_HWCAP_POE] = "poe", }; #ifdef CONFIG_COMPAT