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Sat, 28 Oct 2023 16:13:56 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id u17-20020a17090341d100b001b8622c1ad2sm3679345ple.130.2023.10.28.16.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 16:13:56 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , Alexandre Ghiti , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Samuel Holland Subject: [PATCH v2 11/11] riscv: mm: Always use ASID to flush MM contexts Date: Sat, 28 Oct 2023 16:12:09 -0700 Message-ID: <20231028231339.3116618-12-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com> References: <20231028231339.3116618-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: D9D44100002 X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: x19zccd3iafk4krjar9rgfc9qaoyi4wu X-HE-Tag: 1698534837-606712 X-HE-Meta: U2FsdGVkX18szvFvj1OSAuLE570FNOsDueyq1NWtjF2vOCBhvYURzpi72c1RsE/eEInzmhpU9SAFZZMs6yUlnZN/h3+XMDb/DlWKSqkxPSmo09I4xDj/IGe3I+BnO8sUSrbDUJJTLl6kg9g6E7OseBSS2rIOa4AfVU6N+iHu2v6K1DufJrhlj17m60cVgzHt2lw5RfJ6KNE9QK9lWXxpVcn6N5+y5Nj+nTc8PmMtKhzGDbU4KmKl7Mxtzq3SI1xKQ8CrkHmWz2DDoGZz5+Hzy6BBz31/9SiNsUFssNkzrFcB+e9Seuv7OI5SasGYbxeYQcuiU3c/bfO+ppMTTHPkUD7qcnAAPK1E44K9jbfBnIR9QYlF/w4QJ6zr94vuxu4N4BHnx8UOStSlxX9184/WbYVwmRXfqQ6WI7lPBMWj4SnvfZzuk37UBx5ZEWpy/ub1Db7LCJwWKj4wYPSDknP0V6YkHH7aBR8yJn3FSeyNQh1+mIIePq4K2dKNlOYhSN2USB/ijBZwWoWV0xzjST6RkEBrJclOMYBhExL0WLXk4jk89L4eyCvm8q/DertYApg4d112HGnqJT1VGLxhYWmul+risFxft9mLmu5JkNC04Zq36tCg2p0PfJKDtVyw1TwQugGdGnyDcA0O51CHrbP1twvuZabihpcekW26NFLWLvAu7B2iDoOZH5ZxGe8csGLAwnxLWcF4W6juUPnG9WWVK70ylgS86e4Ju4feltytfZ0OGmj62WjxhvWYXoOvaC7Al9cFG4GOVO4W2o6/4yX+OUvbciMUbjikJp/FPZoKi4NmTmH3nfZvoXtk43f8RLbvtxwSP9wvB/jJdGqjGqljTH0iUlAmFTEYrm8hGbquUTUzpvqAvQR+2QWeKngFEt1rpf5WzN3gzOvsb930OSdhlgjY5Fa3YS8mN9ELXNHyHLs2arFFSVzegImeezpy/EIZHxpltnoMcNEZjJdLOJB hwjfNmQ5 x8qXB5JSAuAjTptOfU2cLwXR604gSatn0EZH51Qw1rs5Nd/jY/78xiVQgeh4eTDIU0Vp0W5jsZoHXz5NUcE8OIoYPT1NuP5C9Rdhdyapzkf+zbTS/ulgRdAGx/49iLN/cru72sowX1O+etIUM2caPjtSCvoZKxCv3gp9beBR4e3ntnTb7VOCYl9e1zk5/WTGhCSzLu11RcKkn9OvzyauoAPppbVUwIp7YykX8bt+tWmGrgIsWc3a6TKwiq/F09XG5Tc3E5+6j7X75dD4ubh/twAw42/3GRGdFMkPaya8eXTetoq8PU+WU3LO0bzuvqkmk7XLcRLETOKdx7/Fu/NZXqsG/R0CHTH9ddX0cUi2lndobytBfHB0zJAxFnBSftLl0uG4kdRQnsXLoDiGIP57qR71K+NuX+2lmpTgBNPXJAt+3j/X1ycF0/JgvEQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000022, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Even if multiple ASIDs are not supported, using the single-ASID variant of the sfence.vma instruction preserves TLB entries for global (kernel) pages. So it is always most efficient to use the single-ASID code path. Signed-off-by: Samuel Holland --- Changes in v2: - Update both copies of __flush_tlb_range() arch/riscv/include/asm/mmu_context.h | 2 -- arch/riscv/mm/context.c | 3 +-- arch/riscv/mm/tlbflush.c | 5 ++--- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 7030837adc1a..b0659413a080 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -33,8 +33,6 @@ static inline int init_new_context(struct task_struct *tsk, return 0; } -DECLARE_STATIC_KEY_FALSE(use_asid_allocator); - #include #endif /* _ASM_RISCV_MMU_CONTEXT_H */ diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 3ca9b653df7d..20057085ab8a 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -18,8 +18,7 @@ #ifdef CONFIG_MMU -DEFINE_STATIC_KEY_FALSE(use_asid_allocator); - +static DEFINE_STATIC_KEY_FALSE(use_asid_allocator); static unsigned long num_asids; static atomic_long_t current_version; diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 1cfac683bda4..9d06a3e9d330 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -90,8 +90,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, /* check if the tlbflush needs to be sent to other CPUs */ broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; - if (static_branch_unlikely(&use_asid_allocator)) - asid = cntx2asid(atomic_long_read(&mm->context.id)); + asid = cntx2asid(atomic_long_read(&mm->context.id)); } else { cmask = cpu_online_mask; broadcast = true; @@ -122,7 +121,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, { unsigned long asid = FLUSH_TLB_NO_ASID; - if (mm && static_branch_unlikely(&use_asid_allocator)) + if (mm) asid = cntx2asid(atomic_long_read(&mm->context.id)); local_flush_tlb_range_asid(start, size, stride, asid);