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Sat, 28 Oct 2023 16:13:51 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id u17-20020a17090341d100b001b8622c1ad2sm3679345ple.130.2023.10.28.16.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 16:13:50 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , Alexandre Ghiti , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Samuel Holland Subject: [PATCH v2 07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros Date: Sat, 28 Oct 2023 16:12:05 -0700 Message-ID: <20231028231339.3116618-8-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com> References: <20231028231339.3116618-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 4E34116000F X-Rspam-User: X-Stat-Signature: 3rtc67xjywtipumfc71y1ayy33wdi8ei X-Rspamd-Server: rspam03 X-HE-Tag: 1698534832-539079 X-HE-Meta: U2FsdGVkX18/GZrntRFsCZEche/R1tVU1IFU+e8KS904iCqpEI9hMxi5D+o7bfcNywcU7pVXrBMY+cZD+HjKJJO8rVwuo5ykp2TqrMz3QJeN+hGPLbUg9x+8M5mHGCTElvKC6BCZfoKVHdyfFj7TPwE9NRK0UG/Zv6xJKY4p/5dZOz/n1SWJG2zv6aPHMyi7CCC7p2jLNBnhhK/jSwmVan9IZ7XRNQ1tUhMdv7Kw7KyPpBHHh+66Htw5LzEXWzZns//yy9GJaAcyig6/nqsNHcjC9VJW/RFuL4VKMilvQgXfUzFdwa3AgIcillhkV99qQvAvsVGK28jWS34csAgEYll31adPBIpmeX0mupV2pzcn20iHMS9+SarGdv6FrMMypCyTO0y+Owk8c3i4oO2U/0WENfi2PbuDvl5+SyWYxVGAJS+iqtLlXgQK6F83PJLuHZLCvZZ5uB/l49VCiYEJhaBN17zgkwqIYGrBsx7+gBQeb+JlZNJBrfQcG30nGy3Hwxjx8Xl7/lEYpcuH6shEMP4dGqMPQMTEuEluREXh7yvp0AfdDGXbnWxQgdH0UhAr0uJi3t0ftvptng8/3wMgJjEWvwWxJNCLwhXHgZORFnRX36H0vzWHRzRj5inQVIiwqWD6QSA0YI4Ke8fHoYFdlioTk3psXcBkFaU9v3FHfoP+XzZ9AxXY5TlC8xU/KvfKX1aKCbfwFxjJ5j1+wEFPCpEkr2Q49SxclfTsWkN00OQ16DbSQAquXeKtE/1Emgj+3GjyBDWFFHunCswgy3l5UHZjlpkgSJ/t9IXBFPNgDwLNbiAzg/KstdDi/h/rR5zLcJFUGkxfsZfGaVggY3o8KF2mk0ouRPpLvA0JEJBDpgRSAWTAuctkbwvC5CzlzNBtKm/dhRELbI5cfCRlTvzSx2G3BGWs/C9NIv4GwzLPT1Eq3jWiyuV7LhhGKkF/yV2ZIvYEoAKfvU7SVexp29x /MiZC+R4 2UN6cw3bk/rNsZm7ENjfwcuuk82ceOX8G7UTICusUXvMw0e8yE9wEWe1WZJzsYpW7hlp7jFy93OF76JE3Z7qBeurXgXmsXCtPhwdZhvK/UxamdqTFrbwm8YoDEG2uUViCC61+sO+aVlDgMpb0sMr8wQu/HrLbDZCcuOT76ciyYEi52U+jmIY2dvL7qkCcSZS21rr0z6FVAqPSX3irzDleFuGgBfwMWiBxs/Ie957J9HxAKLlSBTStTQVn8ihM+Vgua4DPua+3UJn3AGJIXxPQiD4KT+IPUvufGVxSlGIEGcG6E0KG+ixqB3GpFHIfpkEOxe0GK/IcFhrNFeEazN4DnzIKi9374LI8XFkts91A0zdqCv0T8FaRJpcpEQRSD8Z7TuMZaxVn2CBGo/Q= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000003, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: When using the ASID allocator, the MM context ID contains two values: the ASID in the lower bits, and the allocator version number in the remaining bits. Use macros to make this separation more obvious. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/include/asm/mmu.h | 3 +++ arch/riscv/mm/context.c | 12 ++++++------ arch/riscv/mm/tlbflush.c | 4 ++-- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..a550fbf770be 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -26,6 +26,9 @@ typedef struct { #endif } mm_context_t; +#define cntx2asid(cntx) ((cntx) & asid_mask) +#define cntx2version(cntx) ((cntx) & ~asid_mask) + void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot); #endif /* __ASSEMBLY__ */ diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..43d005f63253 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -81,7 +81,7 @@ static void __flush_context(void) if (cntx == 0) cntx = per_cpu(reserved_context, i); - __set_bit(cntx & asid_mask, context_asid_map); + __set_bit(cntx2asid(cntx), context_asid_map); per_cpu(reserved_context, i) = cntx; } @@ -102,7 +102,7 @@ static unsigned long __new_context(struct mm_struct *mm) lockdep_assert_held(&context_lock); if (cntx != 0) { - unsigned long newcntx = ver | (cntx & asid_mask); + unsigned long newcntx = ver | cntx2asid(cntx); /* * If our current CONTEXT was active during a rollover, we @@ -115,7 +115,7 @@ static unsigned long __new_context(struct mm_struct *mm) * We had a valid CONTEXT in a previous life, so try to * re-use it if possible. */ - if (!__test_and_set_bit(cntx & asid_mask, context_asid_map)) + if (!__test_and_set_bit(cntx2asid(cntx), context_asid_map)) return newcntx; } @@ -168,7 +168,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) */ old_active_cntx = atomic_long_read(&per_cpu(active_context, cpu)); if (old_active_cntx && - ((cntx & ~asid_mask) == atomic_long_read(¤t_version)) && + (cntx2version(cntx) == atomic_long_read(¤t_version)) && atomic_long_cmpxchg_relaxed(&per_cpu(active_context, cpu), old_active_cntx, cntx)) goto switch_mm_fast; @@ -177,7 +177,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) /* Check that our ASID belongs to the current_version. */ cntx = atomic_long_read(&mm->context.id); - if ((cntx & ~asid_mask) != atomic_long_read(¤t_version)) { + if (cntx2version(cntx) != atomic_long_read(¤t_version)) { cntx = __new_context(mm); atomic_long_set(&mm->context.id, cntx); } @@ -191,7 +191,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) switch_mm_fast: csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | - ((cntx & asid_mask) << SATP_ASID_SHIFT) | + (cntx2asid(cntx) << SATP_ASID_SHIFT) | satp_mode); if (need_flush_tlb) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 0feccb8932d2..1cfac683bda4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -91,7 +91,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; if (static_branch_unlikely(&use_asid_allocator)) - asid = atomic_long_read(&mm->context.id) & asid_mask; + asid = cntx2asid(atomic_long_read(&mm->context.id)); } else { cmask = cpu_online_mask; broadcast = true; @@ -123,7 +123,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long asid = FLUSH_TLB_NO_ASID; if (mm && static_branch_unlikely(&use_asid_allocator)) - asid = atomic_long_read(&mm->context.id) & asid_mask; + asid = cntx2asid(atomic_long_read(&mm->context.id)); local_flush_tlb_range_asid(start, size, stride, asid); }