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Tue, 21 Nov 2023 17:08:22 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id bn5-20020a056a00324500b006be047268d5sm8713961pfb.174.2023.11.21.17.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 17:08:22 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Samuel Holland Subject: [PATCH v3 4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros Date: Tue, 21 Nov 2023 17:07:15 -0800 Message-ID: <20231122010815.3545294-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122010815.3545294-1-samuel.holland@sifive.com> References: <20231122010815.3545294-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: AA06D100013 X-Rspam-User: X-Stat-Signature: xcgzf6jghbsjmjfk5za3qh4xdyamr4hd X-Rspamd-Server: rspam03 X-HE-Tag: 1700615303-141739 X-HE-Meta: U2FsdGVkX18wbTWypqKnWlK5fbX5yffSD5CSnbOZSI2SOUoz/Aqz8mMMmbo3SRnoGzKTqNjT1zMEEBKTQhZSLd2DVJjy1YRBBJkrogUWr4U1f/Cu2A0ZHr8+8yry3dBcaEQdxt71PgAONywDgYlxXTjGpci5WmzabQdwxwxxGEuI/4ixMXCyZ6tELcBTRDlMsAvuQnMUK32rKFePBz4+Ym/I84qmaXICvF5j57NgJHMTWKkFo1FEkf1OnLGNG1DSbjBRd1r0h8fwG2M64FkL9azhxlsrwnSbKTvDz1YAwaZFqNIMWm1afuj88ZiaRpBWh3o2+orxaPm+ucXCrCHobUwYHa2FATWDhoUyZDJhwFtvASV3uly5uppN3sVzN2CSdRpxTzDpQxjmN7mgIwGjRXD12+a8v6ZM59k3gsYVEqslZgFLoXrOb1EHzQi3Nh2981MOSt+Byteta5VxALjfwZm+iKMIPjrJ6AX68ge/kXTwKcPxIRtQhdHfwceZSzNO/a9X0qlo92biu0EpBCJxV90S4NgKWEV+H+O/uOsJDI5430qmLHKYOVshFJWBeNVFdNkFdsl6U4WPLSDbX+nMglA3I3KbJqT3S6ABKH4tiA2sEihNtae/CSCaCMvbNJMzz/A3u+fuUa0ZKDWOc4VRQdOEC79MSU5Q0vJN/+6n5w8w3RmauyjYz+dfEcJLoNGt9wWvSEYYNOcXpo00UrALmkn7bhMCPVnxsYv8F8gppZcPGJKiJBBrOFV5LmJ8RAY+pnNWyx5Ia/NyI+P945VjzPHwsXMZ8GRH0ZuKWs4CdHr89cNPN7QzcRKbVtuMHwW6GZbZAeoI/4O1pEphQ6wREY8LCpOJCT7KsAq1prAp4hz7un+ehzyIeJ0Xw509THuNBqDXlxDe0lyLBuTnhc+VFpdeHC2vHNam+YvrimM2Qm1LKf2CrT9Q41rCxENexkJBUdhAOCA5lU8j4XVBYUQ VkdxR31q NV/wvyl+5wIQuHBnSneaA1eVfoLqF2tSuc2YGlkRgACLwUNOZcXq+xYatI6RCjnO+Vgw6sx3Dku+E7lq22wVGMl5xLWT787lZyep4gP9qIXpPmjbGLCblcgrj1sU3AlRFZkXrQ92IlEmdBAKextg9bibCSDTtd2oRFInTlTJhb1a9+9O06xofUThaNEcD7bWAqG/5CUybmV32Mf1kRSHNFwZZylxfyw45Q7SAmvcs+nvhhrYN/FTzYKOuJYjehf2FI+mSb3dZoZx3G1p5HbkAxelHUJXZfBLr1FgW9c36b+Gfvku3dzk5EFaXyu0ak7FCLe1iAjHskRebJmBy47OCz3SS8V/UwnF3FvNdDSMrtU5brn5XBf6akQsheQbjbFZneti9d1/TCuk5yDA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000005, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: When using the ASID allocator, the MM context ID contains two values: the ASID in the lower bits, and the allocator version number in the remaining bits. Use macros to make this separation more obvious. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/include/asm/mmu.h | 3 +++ arch/riscv/mm/context.c | 12 ++++++------ arch/riscv/mm/tlbflush.c | 4 ++-- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..a550fbf770be 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -26,6 +26,9 @@ typedef struct { #endif } mm_context_t; +#define cntx2asid(cntx) ((cntx) & asid_mask) +#define cntx2version(cntx) ((cntx) & ~asid_mask) + void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot); #endif /* __ASSEMBLY__ */ diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..43d005f63253 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -81,7 +81,7 @@ static void __flush_context(void) if (cntx == 0) cntx = per_cpu(reserved_context, i); - __set_bit(cntx & asid_mask, context_asid_map); + __set_bit(cntx2asid(cntx), context_asid_map); per_cpu(reserved_context, i) = cntx; } @@ -102,7 +102,7 @@ static unsigned long __new_context(struct mm_struct *mm) lockdep_assert_held(&context_lock); if (cntx != 0) { - unsigned long newcntx = ver | (cntx & asid_mask); + unsigned long newcntx = ver | cntx2asid(cntx); /* * If our current CONTEXT was active during a rollover, we @@ -115,7 +115,7 @@ static unsigned long __new_context(struct mm_struct *mm) * We had a valid CONTEXT in a previous life, so try to * re-use it if possible. */ - if (!__test_and_set_bit(cntx & asid_mask, context_asid_map)) + if (!__test_and_set_bit(cntx2asid(cntx), context_asid_map)) return newcntx; } @@ -168,7 +168,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) */ old_active_cntx = atomic_long_read(&per_cpu(active_context, cpu)); if (old_active_cntx && - ((cntx & ~asid_mask) == atomic_long_read(¤t_version)) && + (cntx2version(cntx) == atomic_long_read(¤t_version)) && atomic_long_cmpxchg_relaxed(&per_cpu(active_context, cpu), old_active_cntx, cntx)) goto switch_mm_fast; @@ -177,7 +177,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) /* Check that our ASID belongs to the current_version. */ cntx = atomic_long_read(&mm->context.id); - if ((cntx & ~asid_mask) != atomic_long_read(¤t_version)) { + if (cntx2version(cntx) != atomic_long_read(¤t_version)) { cntx = __new_context(mm); atomic_long_set(&mm->context.id, cntx); } @@ -191,7 +191,7 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) switch_mm_fast: csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | - ((cntx & asid_mask) << SATP_ASID_SHIFT) | + (cntx2asid(cntx) << SATP_ASID_SHIFT) | satp_mode); if (need_flush_tlb) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 27b3744b5673..23409d70440f 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -91,7 +91,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; if (static_branch_unlikely(&use_asid_allocator)) - asid = atomic_long_read(&mm->context.id) & asid_mask; + asid = cntx2asid(atomic_long_read(&mm->context.id)); } else { cmask = cpu_online_mask; broadcast = true; @@ -123,7 +123,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long asid = FLUSH_TLB_NO_ASID; if (mm && static_branch_unlikely(&use_asid_allocator)) - asid = atomic_long_read(&mm->context.id) & asid_mask; + asid = cntx2asid(atomic_long_read(&mm->context.id)); local_flush_tlb_range_asid(start, size, stride, asid); }