From patchwork Fri Nov 24 16:34:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Gouly X-Patchwork-Id: 13467921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29375C61DF4 for ; Fri, 24 Nov 2023 16:35:43 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id BB57B6B02A9; Fri, 24 Nov 2023 11:35:42 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id B656D6B02AA; Fri, 24 Nov 2023 11:35:42 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id A2E0E6B02AB; Fri, 24 Nov 2023 11:35:42 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 931516B02A9 for ; Fri, 24 Nov 2023 11:35:42 -0500 (EST) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 70C1DB62BE for ; Fri, 24 Nov 2023 16:35:42 +0000 (UTC) X-FDA: 81493398924.12.2837104 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf27.hostedemail.com (Postfix) with ESMTP id 7ED8140027 for ; Fri, 24 Nov 2023 16:35:40 +0000 (UTC) Authentication-Results: imf27.hostedemail.com; dkim=none; spf=pass (imf27.hostedemail.com: domain of joey.gouly@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=joey.gouly@arm.com; dmarc=pass (policy=none) header.from=arm.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1700843740; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IgvlMM1MG+re8vq8iDRIklLV7500gVA4lIaOLAoiLJ8=; b=kgxSgIudobJ0AkqbUw7Mp7igAVTruP8ExxPQ3Gg0EibYH6DD9Mw3DasITXL4AnRHLioKry k8rwtxDfonUXBg35FtgYZUeIByQFqGha4TxpDkc4FhYJ5jJ2XCI1Gjp64bic+/RqF0dUoR mL4mY6aizw2rsOHohWTEtf7TQ1dDVCk= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1700843740; a=rsa-sha256; cv=none; b=7z8LPkchS17IU40VYwESOjg8R/v7HpypT0t06VZ+xwhbeXOwUCzfWFqWS3PbG5GQOMsTzD eFTNju+qbeI9LZzcAQui1ujsBcxd8XXiWyZKdYfCLvC+pU+0l2yyvKkUUwNf/++fXzw+wU Isf2Spk2E/3Xr6J0MRhXqbMkXwH1WO4= ARC-Authentication-Results: i=1; imf27.hostedemail.com; dkim=none; spf=pass (imf27.hostedemail.com: domain of joey.gouly@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=joey.gouly@arm.com; dmarc=pass (policy=none) header.from=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D9A31063; Fri, 24 Nov 2023 08:36:26 -0800 (PST) Received: from e124191.cambridge.arm.com (e124191.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CF433F7F5; Fri, 24 Nov 2023 08:35:37 -0800 (PST) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com, broonie@kernel.org, catalin.marinas@arm.com, dave.hansen@linux.intel.com, joey.gouly@arm.com, maz@kernel.org, oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, James Morse , Suzuki K Poulose , Zenghui Yu Subject: [PATCH v3 07/25] arm64: enable the Permission Overlay Extension for EL0 Date: Fri, 24 Nov 2023 16:34:52 +0000 Message-Id: <20231124163510.1835740-8-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231124163510.1835740-1-joey.gouly@arm.com> References: <20231124163510.1835740-1-joey.gouly@arm.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 7ED8140027 X-Rspam-User: X-Stat-Signature: nbzenr6ih4sqoutzd7oadah6dn57x7ek X-Rspamd-Server: rspam03 X-HE-Tag: 1700843740-11245 X-HE-Meta: U2FsdGVkX1/90hby0UmZKBOme5D/KDogJxe1S2NL2M0qPof0VyWn+zh/VqiVpiBcsYFt7stLNqFoWmw5nOzzmc4JAba4Qf4dtLsRloMt7NT4coG+I/DYGN+5JWDF0Ikg6mw86pUUshx46Nfbht/VcGKoL+qULonf8ORGUcpz64D2hTTcrLEBH79dovZCls3uM2ipL71DmyOVD/qYSgUK///TtkcJzt/XfBgvpWReBgtO62rxJyV76SZUCthNXqCg3FXfscsnZdzlGXsxmf+6pLt3Su6gWiKJ2SXJtg3F7ZGu/qHixUR9zz2AK3YSy/v95p38Cv8RWJlpRI/4UdboLL+eTkwuc5sB+a8NVfKMC3Ahx5CplIjVtvF1m35pRPrPl1jc8cvry6sIIAvRiEifwZojYlc5jpJhm1M3x9PTfGb0jcFqwdA2k3Lf9f11bQHzP+gITXT/aBNYhMLU917DGrI+2Vk6FB196uQRSxM7k8d89d33BlxPYBVIJ6e4onKeN6bNDepaSyJkiCH07iCH8MvWhmhZ4cMRsjdWankuAf8bahy+jYhRPD8rjOScIDFuO1SQpezQbmwIZ/TM55GNr1fzaApNUPexhW6OO8/fBehkFDW6W8zqDGng8AtcQO0tpqLGITxBJ/qe3RY03BGqNTliddc7Ae64NVy9BZQe6n3T/zpsn+dt/YJlO8HQQ4N1EbOTD6GWshY2Ouu1t+kb/fgKl+yPUd5Gpvhwin5/onJDADtb2a5pw7MRGXznaZvi9aoB4jS4dGe8OOdBC++K+0f72lGH6yJciH0m48BXRl9w32gZeLX/o2BnMTAHlvAtSxkmRPTAdse9iWPBPgPW6+/tpF71thnTrVMB4VSIb5FENRgsu64NMJKuBT7CPj8ss8uS/UgmIUSvcaUhMebVkOBJlmJJSeg3wWli8vMP39WtXAoaqPH2u+wMvPPIsk+PHdIavv9uqYdlcIN8ES4 8Ye08Ix2 tPM6fSThcHZh8AO7DpMK40iMLedn7D+aMxbSgzlnZTZbG8D0SMTTWhwIhtqqo02bmrh2vJp78UPXYQRs3SsHmLmUByDP02VN6VEOoYkwrs9mG7FTd7PDhiY+NdUqZxYqJhuho16vBqWEAICydEncmJiu+uu6QmYgaC5jkSz5AI5w/YWtneRojKeiX0DHXfxYZz9hm2Zrjcj4NPABs32T/XBtxjHWr+c5+ylBy X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to check if the CPU supports the feature. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon --- Documentation/arch/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 20 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index ced7b335e2e0..fe7350a66cea 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -317,6 +317,9 @@ HWCAP2_LRCPC3 HWCAP2_LSE128 Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011. +HWCAP2_POE + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index cd71e09ea14d..9a1aa1e5e25c 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -142,6 +142,7 @@ #define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16) #define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3) #define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128) +#define KERNEL_HWCAP_POE __khwcap2_feature(POE) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 5023599fa278..69f09521b553 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -107,5 +107,6 @@ #define HWCAP2_SVE_B16B16 (1UL << 45) #define HWCAP2_LRCPC3 (1UL << 46) #define HWCAP2_LSE128 (1UL << 47) +#define HWCAP2_POE (1UL << 48) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 00b6d516ed3f..02169cb3b84b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -402,6 +402,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), + FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), ARM64_FTR_END, @@ -2242,6 +2244,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); } +#ifdef CONFIG_ARM64_POE +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); +} +#endif + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2737,6 +2747,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_HAS_S1POE, .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_poe, ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif @@ -2889,6 +2900,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), #endif /* CONFIG_ARM64_SME */ +#ifdef CONFIG_ARM64_POE + HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), +#endif {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index a257da7b56fe..5515c50f5219 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -130,6 +130,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", [KERNEL_HWCAP_LRCPC3] = "lrcpc3", [KERNEL_HWCAP_LSE128] = "lse128", + [KERNEL_HWCAP_POE] = "poe", }; #ifdef CONFIG_COMPAT