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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF00017098.mail.protection.outlook.com (10.167.18.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7159.9 via Frontend Transport; Sat, 30 Dec 2023 16:26:58 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 30 Dec 2023 10:26:58 -0600 From: Michael Roth To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 23/26] x86/cpufeatures: Enable/unmask SEV-SNP CPU feature Date: Sat, 30 Dec 2023 10:19:51 -0600 Message-ID: <20231230161954.569267-24-michael.roth@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231230161954.569267-1-michael.roth@amd.com> References: <20231230161954.569267-1-michael.roth@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|MW4PR12MB7481:EE_ X-MS-Office365-Filtering-Correlation-Id: 58f029b1-4130-45cf-1d1e-08dc0954255f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2023 16:26:58.8035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58f029b1-4130-45cf-1d1e-08dc0954255f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7481 X-Stat-Signature: yuawi773qqcfkudyb7rrbnbawnjsnymh X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 1762180009 X-Rspam-User: X-HE-Tag: 1703953621-134466 X-HE-Meta: U2FsdGVkX18CEn5tvNXgkzC6YOUvPxCjqiv+Ir1LKQcfhaMfBsB4hZRniKktin4KOKVSQhuZIzBLLm5PoPU1b5UXr7dlK6a2xMFaUPgksfxcmmM1HVwMBjzydbnWkNdRpNNB+cQtvW5nokfsTA6JGEVLPMhlulGBgCyV7PLwchKh1s/4FNd9I/bwUIpwHbBLrX2nqgQNvRQ6LAnKYDqAMmiAjekj8aUbj3Pmd+XTtEpt87ZCMS4vIRMsORSwDn/FUT6dRyJRXLXP4sZIq82wMV25rrFAePADkORA9v6bKQXyl3RIC53kbpQZOcgx0HVV9qOrZCIR8k5CWk7nuG9hOetJ52HC7bzvk31UXAPO87dszAUj/DYKGRzfMa0I7ywETwv3r+zDsXmCU8HubnX5D1+nsaVk1YlmTnh9gOF8N9EQrBvLoxPzuzJNvoWAnhktKMe7XyIlpjnd76ZB2JLEeH7m2CDMEnYf555AhK7lpwv+FNV695bgVWH6X9vEtqo54xVZSEvoHw0gZp+/LC5bWbVJbLl9mkhIWK4/YczNug3vYw7G02uO7txBO2lH0zXLytYY9Itcrs4tY7dZH6YjKtCLfepZsgmo4vHpnCSS9qkJvvq7ZfnEjY2bX0VNRiVcmJWmlHXTJ5oiVKO1ze1DvC2ohvRFOIJAv9vu0e3fJIkAB3A3kmmuEtF5NmwU4/cTxGWFcmpYy7SHuIk1lm6ICJgWBy1tVuwkM8oVyJ+bmw1hYCpr73XMuVJ9IJsKZQ7ucQAanexzuT7sPIGEHW6OyszkuVn9gs2O5csaoahHbtKzayL6vmKs6LFzvCGo5ZJvOmAPZGKoS3YPanKOd+gMvcl4mOvZObASJwZjDHf66boMbhdhQ+4SiK91ZatojAjPdKuffk36rkFQq83/xboe4KNMpDRR9z4aj/jsFtNMTTnzTyTKlbYKNXDECaIT4KZqVgVpXgZejHqFhqDeU4k V1w== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000027, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With all the required host changes in place, it should now be possible to initialize SNP-related MSR bits, set up RMP table enforcement, and initialize SNP support in firmware while maintaining legacy support for running SEV/SEV-ES guests. Go ahead and enable the SNP feature now. Signed-off-by: Michael Roth --- arch/x86/include/asm/disabled-features.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index a864a5b208fa..3332d2940020 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -117,7 +117,11 @@ #define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31)) #endif +#ifdef CONFIG_KVM_AMD_SEV #define DISABLE_SEV_SNP 0 +#else +#define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) +#endif /* * Make sure to add features to the correct mask