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Wed, 24 Jan 2024 22:28:21 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id t19-20020a056a00139300b006dd870b51b8sm3201139pfg.126.2024.01.24.22.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 22:28:21 -0800 (PST) From: debug@rivosinc.com To: rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com Cc: corbet@lwn.net, aou@eecs.berkeley.edu, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, guoren@kernel.org, samitolvanen@google.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, waylingii@gmail.com, greentime.hu@sifive.com, heiko@sntech.de, jszhang@kernel.org, shikemeng@huaweicloud.com, david@redhat.com, charlie@rivosinc.com, panqinglin2020@iscas.ac.cn, willy@infradead.org, vincent.chen@sifive.com, andy.chiu@sifive.com, gerg@kernel.org, jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bhe@redhat.com, chenjiahao16@huawei.com, ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org, baruch@tkos.co.il, zhangqing@loongson.cn, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [RFC PATCH v1 02/28] riscv: envcfg save and restore on trap entry/exit Date: Wed, 24 Jan 2024 22:21:27 -0800 Message-ID: <20240125062739.1339782-3-debug@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240125062739.1339782-1-debug@rivosinc.com> References: <20240125062739.1339782-1-debug@rivosinc.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 6B681C0017 X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: ebi8wxpsnrf5j5yatp1naf1uaqe5afdj X-HE-Tag: 1706164102-854973 X-HE-Meta: U2FsdGVkX18InXbKz7BflU/3GocPp8gnAFgyMv34yxBR0BRdZ3tJTYzkJdScttf0btYhgoHVx68kpBJ1+IUPBHKCZQ2u3Z3EOgpNH9Pup2l+uYMVpVSUbEvzB1Ofuq+g0/1NDu0f+HhFOgqJ75otgjMqPii3nE6ygJ7PyESSRoIGOt5QTMQ5VJUnwoi97yPaJJfHTqsEVhs/76fXdcAJyzIpsq/JZE1GKozVXxEwkpJaWeyJIAF03mDUNNcHjW2PdZO06nY5hFal4NAEpWztc8Xxm5FBKKmbMipai7mehBQup0zypddI53xMIRpJEJUozLQpVYXbeE8upZ4CQ3PICdseBhQtGo7V0dk3iJkExGGYangLGgrpMljUESiljBAe9MsMf8KWopc6cik8uk5V0qHHUwe0sCLfVB4vQ89Unv9cp9l1nrdU+LCPmaNxFD5fhK6wY1cvL6O7r2ij0poO1TcKWyKNpn2gLgOe4/6lEHGc/FCEa4P3jzR6hYd/WGWRgTihAB2iqVMuZiPEhTYwjT4MMqCXm4c/3yHdt713idCNME8S04arqFbSwtxKIjD5zia5F7kGBaL8+eW3wjhmKtvwA8/SnPYspKwyi/fyt+gVwE9LSd1t9T8gGyr96S+3n5k4T6YRRIQlGNAms4Yo1FziE+7T5ajBeyvnTVu6UmPMWENPu7eP7NFElWZiF2ajCrKh/ZF+8yKJA3Q4bKcHkjdvnyFf8vg8rNwOeKHUsbQ2owpAHT8QuDHAfgLTCPPUgtQ41qgACyRlqKb+PCOJqN8TU6FfOahGHiza5yULrpBM+aT1F6JsOOMNh5KwxKEOkr9XhPPSQ0TyhVo4rBkIm27RcCM2iyfRMXqJw1/vkCy7VOVFQ0uGxa9kEpZutdsCDgvSJR7+kOrLfGj+WoeJf25EzvayIqS/OT7pTqnAGBi0yRf+AIlMRiZoo/sTAfo8wqstKeSCfrD4zEIOJPh YciZu/oz ErujXbqNjTwVeCC3Pa/LKgIz3vGQFC+6vHNprq1rL14kn6BS7GIQYvWxdEP61wmJ+7YjOupG0IMe6b3zazhOWfVPaRi6UH7GZsQPL7Ol5eWqKEg4OWM1hHK2WNLjp46vkTKugt5kEKc+6nTP0DKOpD+6WbA+LkfAWWhos32qWFtv4mpqzswSJA7MvdOlEoIgRIScLkJoK6R6Kv2tZsNPEmZU9m8TuV8JeC8IY5kOMOlpXdOMz5hPbPl6WzFHk93iSJVQSvcZ/tzyNj1oXS5mBcJr82NHRarx8PJyedG0yXpR0BOIHqQfoH1hv6dS1/2HD/lng0+TzuLwhqJxZ1NF+yzAsU7C8PTFWXHuOPeFm/JXmtPECiGSf0u85pWO5z7YFeiKiJ8lEb18WbBKnsJ9C5E64LE8eWw/DsnGpBsx50Zd2DWvxgfo7NDETThzzVn+0FiWu X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Deepak Gupta envcfg CSR defines enabling bits for cache management instructions and soon will control enabling for control flow integrity and pointer masking features. Control flow integrity enabling for forward cfi and backward cfi is controlled via envcfg and thus need to be enabled on per thread basis. This patch creates a place holder for envcfg CSR in `thread_info` and adds logic to save and restore on trap entry and exits. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/thread_info.h | 1 + arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/entry.S | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index 574779900bfb..320bc899a63b 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -57,6 +57,7 @@ struct thread_info { long user_sp; /* User stack pointer */ int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ + unsigned long envcfg; #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index a03129f40c46..cdd8f095c30c 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -39,6 +39,7 @@ void asm_offsets(void) OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); + OFFSET(TASK_TI_ENVCFG, task_struct, thread_info.envcfg); #ifdef CONFIG_SHADOW_CALL_STACK OFFSET(TASK_TI_SCS_SP, task_struct, thread_info.scs_sp); #endif diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 54ca4564a926..63c3855ba80d 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -129,6 +129,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception) addi s0, sp, PT_SIZE_ON_STACK REG_S s0, TASK_TI_KERNEL_SP(tp) + /* restore envcfg bits for current thread */ + REG_L s0, TASK_TI_ENVCFG(tp) + csrw CSR_ENVCFG, s0 + /* Save the kernel shadow call stack pointer */ scs_save_current