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Wed, 24 Jan 2024 22:28:28 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id t19-20020a056a00139300b006dd870b51b8sm3201139pfg.126.2024.01.24.22.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 22:28:28 -0800 (PST) From: debug@rivosinc.com To: rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com Cc: corbet@lwn.net, aou@eecs.berkeley.edu, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, guoren@kernel.org, samitolvanen@google.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, waylingii@gmail.com, greentime.hu@sifive.com, heiko@sntech.de, jszhang@kernel.org, shikemeng@huaweicloud.com, david@redhat.com, charlie@rivosinc.com, panqinglin2020@iscas.ac.cn, willy@infradead.org, vincent.chen@sifive.com, andy.chiu@sifive.com, gerg@kernel.org, jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bhe@redhat.com, chenjiahao16@huawei.com, ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org, baruch@tkos.co.il, zhangqing@loongson.cn, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [RFC PATCH v1 03/28] riscv: define default value for envcfg Date: Wed, 24 Jan 2024 22:21:28 -0800 Message-ID: <20240125062739.1339782-4-debug@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240125062739.1339782-1-debug@rivosinc.com> References: <20240125062739.1339782-1-debug@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 5736A80015 X-Stat-Signature: ketq5fcfb8fpzcpuzs9rpyk84fs6qhxr X-HE-Tag: 1706164109-732282 X-HE-Meta: U2FsdGVkX1/jBLRQpVwOgwsmYJTYGGAnxtpB+v+mBkXJREtlMGz/nqfDfkhD5CQqgQISdvuoZG873hgH4jJH4JJ61TgQbxASrPRTKnhOPYLOPpdqBdQKVUDylng7NpcB5qeDEsvNguvJLnlc3/GWrL4nXd6IX5217nnF7G4LKZQSpuBj9/oVLAvPrdf9/IdWifv+m58T8nYAkwIRUBTA30DklYNyafvxHp1u4POeBqJQc/1iSCeAqKTRw4VSUDB4O8qeR3Q3Djc0GDPzXD6iByj4I2WrjZny8Jj6M4CK7LQAlMoYfQ68fnZfCiaqe3Av3Np3lQuwpf7yEDfquD2dosfpHcY7dpXiJK0kLuwTZh+d63Uy50fRVWRqT/qWMCrXMx0WPonZ1jJ9NNBgDio+tZNFz36VgFPx764zQilUgdkF7ccSNaRK5jgTMJR257W9n89rUmR5u5B4g9CV4BN+yYhlufPtNZuo0fNUqtn9kLxrlUCQb9ChYNyAU+yq5qwfPqvX9JLqR7R5o8HtCEWOW58t0XvsTPTDs6prN79NVKwUrA82mOm6d38RqayHrMdgKRNRmpDhbgqXwrdaieN0v/ERmOsvV670XKbbiNSKxv8wbhYGrSqwBlRymZHsLD4/Q3rNh88193EleP3wqLqkOkdiS4zkajHMShQn6UxiPDog8oCokPpDAT3xDeqsqpU2zo6HwkE4cNuUMNExte7ec/qruEfIX1lmF57EzprLoZr8/VBWTKRyNtgswakRdNjJYvNfA8Py2iahiz7Sg/uLLXHp2PY0R4NNENRUhtVphlQ34oUAeNIvlIbCXvx5J9lHuFiARNVxwPgP8PzMbnl03WGCkzpDpvgkOWmRmvjDx0wNsBAqVlFhMhQsmguq+k1E0LsDrd+kgjSkmZ+OKfcBoyQx7Bs8TD1jLM2/ctFUhpnqnnb4IMlcB+oSS1K273ZMgNf+Wci1oxCm3NI6Ewk Yk5hDp26 FO7+wQsGY6qVdrqAgFR5AGBvKJbJf1VxtCz8kuI6VyFEEXRvGC9YC3p6he7Kj8Pa3/7xaYoZGSWoRwR/faNUJF6EMOAGgUDMwCAJ2kdSmYkXR+vhKPIcxkEJOtIWxxxRETagypUhxVG5UOwBhdo7DPtbou5ZKT8+xJjq5LXgJozRAuEcJwIZRdqgVPIxOd3AOQK/tnp+a8eDH/SjurgydDuOUEzZaoAHmgF8/LKVBVmmQUzfEc10dzKKWZKvi0+EVnopWA/PO2yFZdBLGRcnTudZwVVgJykSJ2nTWOgkYbzeyIm3JMWcCf4GfpABPtCVpDu2HeopOJ9LB1QatS3vu/qMPmebY0rPzChl9ZzrR9GV/V4FTAbMcuMMERulI7I79mlGe39ggBdcTFxdvXeK4w2yGSCYMqxR7uIIgtR0jiypKj1CTsI6GH66hYVRi5EuZqoIZ X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Deepak Gupta Defines a base default value for envcfg per task. By default all tasks should have cache zeroing capability. Any future capabilities can be turned on. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/process.c | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index b3400517b0a9..01ba87954da2 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -202,6 +202,8 @@ #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) #define ENVCFG_CBIE_INV _AC(0x3, UL) #define ENVCFG_FIOM _AC(0x1, UL) +/* by default all threads should be able to zero cache */ +#define ENVCFG_BASE ENVCFG_CBZE /* Smstateen bits */ #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 4f21d970a129..2420123444c4 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -152,6 +152,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, else regs->status |= SR_UXL_64; #endif + current->thread_info.envcfg = ENVCFG_BASE; } void flush_thread(void)