From patchwork Fri Mar 1 09:14:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13578198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1C6EC5475B for ; Fri, 1 Mar 2024 09:19:20 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 49CE66B009D; Fri, 1 Mar 2024 04:19:20 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 4257F6B009E; Fri, 1 Mar 2024 04:19:20 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 276CD6B009F; Fri, 1 Mar 2024 04:19:20 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 13BF66B009D for ; Fri, 1 Mar 2024 04:19:20 -0500 (EST) Received: from smtpin10.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id B55DFC125E for ; Fri, 1 Mar 2024 09:19:19 +0000 (UTC) X-FDA: 81847921638.10.0DEF8E9 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by imf17.hostedemail.com (Postfix) with ESMTP id DD44B40012 for ; Fri, 1 Mar 2024 09:19:17 +0000 (UTC) Authentication-Results: imf17.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="oB/UuS8t"; spf=pass (imf17.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1709284758; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=mB8cpSFUHI2v28tFlR/YUHSb5lk45+n/9IYk3vd50wk=; b=EHKnbpOC8QTOX2kRHJOl3ACZ7xFqz2pm3ijx5juPUYk+HSRjQJf1xpWiwZQ7YL/I3c/dL3 BYhoAowApEd3kQDVMN1hFKyBmsFI/X2Lhcr8PLDTQ5RxrFCmawHEiNTrVKYqTwS9jDHw7h RfUuS8piq2lYOyFsMnCYh7Tr2uoLyTM= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1709284758; a=rsa-sha256; cv=none; b=0o1+tV5I+LgZBCF9jdSblxbI/hDvCRt0jJsTFwEOl5Dg5EbqB/G9LuVI7FjmllAOkn1/bt 9fB8Nf1atDYgofOsEKTQ0fjXb55boZp8umyFnooLtVOgWN9OfuOz+M8MfybMdhe8lV4o8k SMbkWyJdwVJ0ETye1oUfe2s+e+KhyoU= ARC-Authentication-Results: i=1; imf17.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="oB/UuS8t"; spf=pass (imf17.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com; dmarc=none Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-33e12916565so847754f8f.1 for ; Fri, 01 Mar 2024 01:19:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709284756; x=1709889556; darn=kvack.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mB8cpSFUHI2v28tFlR/YUHSb5lk45+n/9IYk3vd50wk=; b=oB/UuS8t/ggi3HMYS8+eKu+6AtVfQjjIk3HCys6DG0qSyY1pPF8jCHoltvnUlpXRSB qQJSc9QoxeKeepQj5/KWq4iAIjuPPpXq4SyKsaJ4M+aZO8j5Sp3pOxjzZcfjpmWX/JBk sYVdf5RCmfYKnJhLGBotDN8fOAcG0aA1NyiCD/FJsKrK08aT37hteqEERc4YuU95A9pn uSA5dMuBmJu0i2q5xt7olRQoCpedBhMexU7MuDe1pv5aJc7sswILytdCwlDbyxGGXE9E vYgjcXD2mReePZiPPu7uq1MT013g4NMPma1cTLs8dcfraoDBWE6GZ//Qr605ALUkt9O6 Cdwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709284756; x=1709889556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mB8cpSFUHI2v28tFlR/YUHSb5lk45+n/9IYk3vd50wk=; b=Ans3k92pVqtdHb9flaUrpSIkZXqiAdUoe9Sc8uFxXVj70u00wZP9vOo7ZUwaiemGMc HnORrYSfc0+AxxzIhyzSmdSSbZ/Q1hAuxnVnJn8Fcpve6jnSaHmAx6lJkCqwoXT/HYEd QxjX16UJxohNo/SiPBD15MtjkJMqaxNroI6hiKC4BykXxrOL9J+4Koyfa2we+svJfoG8 xds5V4MbceRTv1Qh33k2Pdfn2TNhw88H3dnMZgQd138UOdIKgmcsdKuPVNQJHhsvC0SC p61eI7sWgEJSM+GHbK7D/jD3BOvp/Yyu495I4p4CKMtwkI2CwUo3VDLPoPK53wp5k87c bSJQ== X-Forwarded-Encrypted: i=1; AJvYcCUHrbZgTPFupXZ8bWgUdTdQzyjQrEgobB67Z36nUVRMN2Q35nByEwf2FMpvpvOtVaLd1gHJ/YzzAz6OA7BowJkyCFs= X-Gm-Message-State: AOJu0YxsV0PWjAvXBLDLWX1ou4luwF9Em7DkU5xpiwDoMKSJhqKUf8v7 GQiYfS/0UEwmKFGCWZ6aEDn0OxwOqoxVvwDURgw1kuEHahSS/Ck7Qh0nejxTuzo= X-Google-Smtp-Source: AGHT+IHpEyM7pTJk28YugLtMmnzHnlZqFOrfhIPrp2GM/yv98BwZmlX0jtBa8/Iqo86IkfuCuT/7uw== X-Received: by 2002:adf:9dca:0:b0:33e:1a3f:44b4 with SMTP id q10-20020adf9dca000000b0033e1a3f44b4mr1239957wre.26.1709284756335; Fri, 01 Mar 2024 01:19:16 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id bv16-20020a0560001f1000b0033e0523b829sm4144440wrb.13.2024.03.01.01.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 01:19:16 -0800 (PST) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH 4/9] mm: Use common set_huge_pte_at() function for riscv/arm64 Date: Fri, 1 Mar 2024 10:14:50 +0100 Message-Id: <20240301091455.246686-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240301091455.246686-1-alexghiti@rivosinc.com> References: <20240301091455.246686-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Stat-Signature: 5ohi4qh6k6qjqrtho6ju1stjagqcpuqw X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: DD44B40012 X-Rspam-User: X-HE-Tag: 1709284757-104180 X-HE-Meta: U2FsdGVkX18cGsFSPJM+DLHDqBQBUWlsAKcx3i439nAlZk7oRoGq0G9kiaE9a705N56/p4ACDkOOky3CHZZ9OhOliSFIIUMe6mDi3b0kfSzPO7I78kn9SWzBGYLMIZu20pF9825gIO552uHPOz/I1UAE3iCM5/NWi1jZ+r3mTKsTi8MonetBzr0rW8Pz+H+4fThD8fzez0sapYeBbDb/8mjPxsx+74gKw/RLgxeveMHEd7vqyCEbKeReVJ4uedZxhmau9sT8Z8wiiVZJghlDmlxoHdZ688vV/Ldi9cGOY8NKqQYIcLrCTkXVLdxByzD2LsRk4iG1v8GIsoOlhQi7pPjoaYLL48W8Sv6rtZcyrRAu5zt40Uci0/YZ0h/fj/SPebwBXw6P8QFLhE+5BV+ysm4NeWFskbhYnTpcKTeA3cRnD1oTm5wzePL8mxAuTro/Wxh7JPNWhsUkLDSjexf8WEgKpiWmcmItSI6CCoQExotOb/HRUFJtZboMNLmVKVIyyk0Yk77VIN6fPzdQL+29AfE1KdDs2A80FuJMqMN03NjVlHzsa8HtmH1Jm0lwVqVdccX0H5O1LzGvOpbYr7mfLt1ZJgGiJdRVJxIfiDcMVei7sut8gvboF/9kS6edPAjdaA9uP9dAXHZ1f8ifloXf5SG0521E7XhhC5myC1OquVPgI59P1V/gCAKm9RVS1pEB6KKzQMa1pG1nA163WaEJ+DJn1wyrh4bgjV/2JqJDlEOXYdYn9WPipjhcfD9xMHUmoz0nXwUOTGN/2X2BqOZZnycr4blo2ko22/5UHXp7VCmtelVgFnqYtvqGpgTYIMnhHNIYo19mM5egu1bwN8klRnpcaJEudCfCbsTfA0ESkFPlj4X5XfxwBRCMHZg5TBrahRY5JBNut4hKdCyVMg06ETkgk81fCjqx1AG2sUtzZafdhT9WescNm5v1WdB8ZIJ+pBfvB7+Urx72i4lxRBU /UVeUfOB D+smCExHCfwOd09pmSx5itzbmKASa5bu/HVIOZF2N+PCYdEIrwU/USmwtQxmoRKYxGPn5B2BV3+LGNq0b/6bEi7c53OWDOCirQw5viSJks0NBM0cpBnW6Iue0dv09NZY5IEbSPTs90lGaA9KF1Z05E6TPPBRYvIdJ6jPpeLOupf7K4FWbszIZ30x75wB4iQN0DNzvK9F40kyv0uChFHVxMe0lnA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: After some adjustments, both architectures have the same implementation so move it to generic code. Signed-off-by: Alexandre Ghiti --- arch/arm64/include/asm/pgtable.h | 16 ++++++--- arch/arm64/mm/hugetlbpage.c | 56 ----------------------------- arch/riscv/include/asm/pgtable.h | 26 ++++++++++---- arch/riscv/mm/hugetlbpage.c | 62 -------------------------------- mm/contpte.c | 58 ++++++++++++++++++++++++++++++ 5 files changed, 88 insertions(+), 130 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 3003a10547de..437e9638b2b9 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -341,9 +341,10 @@ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) mte_sync_tags(pte, nr_pages); } -static inline void set_ptes(struct mm_struct *mm, - unsigned long __always_unused addr, - pte_t *ptep, pte_t pte, unsigned int nr) +static inline void __set_ptes(struct mm_struct *mm, + unsigned long __always_unused addr, + pte_t *ptep, pte_t pte, unsigned int nr, + unsigned long pgsize) { page_table_check_ptes_set(mm, ptep, pte, nr); __sync_cache_and_tags(pte, nr); @@ -354,10 +355,15 @@ static inline void set_ptes(struct mm_struct *mm, if (--nr == 0) break; ptep++; - pte_val(pte) += PAGE_SIZE; + pte_val(pte) += pgsize; } } -#define set_ptes set_ptes + +#define set_ptes(mm, addr, ptep, pte, nr) \ + __set_ptes(mm, addr, ptep, pte, nr, PAGE_SIZE) + +#define set_contptes(mm, addr, ptep, pte, nr, pgsize) \ + __set_ptes(mm, addr, ptep, pte, nr, pgsize) /* * Huge pte definitions. diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c index 6b61714d7726..4da951e81bde 100644 --- a/arch/arm64/mm/hugetlbpage.c +++ b/arch/arm64/mm/hugetlbpage.c @@ -166,62 +166,6 @@ static pte_t get_clear_contig_flush(struct mm_struct *mm, return orig_pte; } -/* - * Changing some bits of contiguous entries requires us to follow a - * Break-Before-Make approach, breaking the whole contiguous set - * before we can change any entries. See ARM DDI 0487A.k_iss10775, - * "Misprogramming of the Contiguous bit", page D4-1762. - * - * This helper performs the break step for use cases where the - * original pte is not needed. - */ -static void clear_flush(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - unsigned long pgsize, - unsigned long ncontig) -{ - struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); - unsigned long i, saddr = addr; - - for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) - ptep_clear(mm, addr, ptep); - - flush_tlb_range(&vma, saddr, addr); -} - -void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte, unsigned long sz) -{ - size_t pgsize; - int i; - int ncontig; - unsigned long pfn, dpfn; - pgprot_t hugeprot; - - ncontig = arch_contpte_get_num_contig(ptep, sz, &pgsize); - - if (!pte_present(pte)) { - for (i = 0; i < ncontig; i++, ptep++, addr += pgsize) - set_pte_at(mm, addr, ptep, pte); - return; - } - - if (!pte_cont(pte)) { - set_pte_at(mm, addr, ptep, pte); - return; - } - - pfn = pte_pfn(pte); - dpfn = pgsize >> PAGE_SHIFT; - hugeprot = pte_pgprot(pte); - - clear_flush(mm, addr, ptep, pgsize, ncontig); - - for (i = 0; i < ncontig; i++, ptep++, addr += pgsize, pfn += dpfn) - set_pte_at(mm, addr, ptep, pfn_pte(pfn, hugeprot)); -} - pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long sz) { diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index ddff4a56e12d..03f8ced8b26a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -533,29 +533,39 @@ static inline void __set_pte_at(pte_t *ptep, pte_t pteval) static inline int arch_contpte_get_num_contig(pte_t *ptep, unsigned long size, size_t *pgsize) { + unsigned long hugepage_shift; pte_t __pte; /* We must read the raw value of the pte to get the size of the mapping */ __pte = READ_ONCE(*ptep); - if (pgsize) { - if (size >= PGDIR_SIZE) + if (size >= PGDIR_SIZE) { + if (pgsize) *pgsize = PGDIR_SIZE; - else if (size >= P4D_SIZE) + hugepage_shift = PGDIR_SHIFT; + } else if (size >= P4D_SIZE) { + if (pgsize) *pgsize = P4D_SIZE; - else if (size >= PUD_SIZE) + hugepage_shift = P4D_SHIFT; + } else if (size >= PUD_SIZE) { + if (pgsize) *pgsize = PUD_SIZE; - else if (size >= PMD_SIZE) + hugepage_shift = PUD_SHIFT; + } else if (size >= PMD_SIZE) { + if (pgsize) *pgsize = PMD_SIZE; - else + hugepage_shift = PMD_SHIFT; + } else { + if (pgsize) *pgsize = PAGE_SIZE; + hugepage_shift = PAGE_SHIFT; } /* Make sure __pte is not a swap entry */ if (pte_valid_napot(__pte)) return napot_pte_num(napot_cont_order(__pte)); - return 1; + return size >> hugepage_shift; } #endif @@ -631,6 +641,8 @@ static inline void set_ptes(struct mm_struct *mm, unsigned long addr, } } #define set_ptes set_ptes +#define set_contptes(mm, addr, ptep, pte, nr, pgsize) \ + set_ptes(mm, addr, ptep, pte, nr) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c index 51ec80cf2028..ebc735f5d325 100644 --- a/arch/riscv/mm/hugetlbpage.c +++ b/arch/riscv/mm/hugetlbpage.c @@ -173,68 +173,6 @@ pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) return entry; } -static void clear_flush(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - unsigned long pgsize, - unsigned long ncontig) -{ - struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); - unsigned long i, saddr = addr; - - for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) - ptep_get_and_clear(mm, addr, ptep); - - flush_tlb_range(&vma, saddr, addr); -} - -/* - * When dealing with NAPOT mappings, the privileged specification indicates that - * "if an update needs to be made, the OS generally should first mark all of the - * PTEs invalid, then issue SFENCE.VMA instruction(s) covering all 4 KiB regions - * within the range, [...] then update the PTE(s), as described in Section - * 4.2.1.". That's the equivalent of the Break-Before-Make approach used by - * arm64. - */ -void set_huge_pte_at(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - pte_t pte, - unsigned long sz) -{ - unsigned long hugepage_shift, pgsize; - int i, pte_num; - - if (sz >= PGDIR_SIZE) - hugepage_shift = PGDIR_SHIFT; - else if (sz >= P4D_SIZE) - hugepage_shift = P4D_SHIFT; - else if (sz >= PUD_SIZE) - hugepage_shift = PUD_SHIFT; - else if (sz >= PMD_SIZE) - hugepage_shift = PMD_SHIFT; - else - hugepage_shift = PAGE_SHIFT; - - pte_num = sz >> hugepage_shift; - pgsize = 1 << hugepage_shift; - - if (!pte_present(pte)) { - for (i = 0; i < pte_num; i++, ptep++, addr += pgsize) - set_ptes(mm, addr, ptep, pte, 1); - return; - } - - if (!pte_napot(pte)) { - set_ptes(mm, addr, ptep, pte, 1); - return; - } - - clear_flush(mm, addr, ptep, pgsize, pte_num); - - set_ptes(mm, addr, ptep, pte, pte_num); -} - int huge_ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, diff --git a/mm/contpte.c b/mm/contpte.c index c3f4b8039b19..f7bfa861c6a1 100644 --- a/mm/contpte.c +++ b/mm/contpte.c @@ -12,11 +12,13 @@ * * contpte macros * - pte_cont() * - arch_contpte_get_num_contig() + * - set_contptes() */ /* * This file implements the following contpte aware API: * huge_ptep_get() + * set_huge_pte_at() */ pte_t huge_ptep_get(pte_t *ptep) @@ -43,3 +45,59 @@ pte_t huge_ptep_get(pte_t *ptep) } return orig_pte; } + +/* + * ARM64: Changing some bits of contiguous entries requires us to follow a + * Break-Before-Make approach, breaking the whole contiguous set + * before we can change any entries. See ARM DDI 0487A.k_iss10775, + * "Misprogramming of the Contiguous bit", page D4-1762. + * + * RISCV: When dealing with NAPOT mappings, the privileged specification + * indicates that "if an update needs to be made, the OS generally should first + * mark all of the PTEs invalid, then issue SFENCE.VMA instruction(s) covering + * all 4 KiB regions within the range, [...] then update the PTE(s), as + * described in Section 4.2.1.". That's the equivalent of the Break-Before-Make + * approach used by arm64. + * + * This helper performs the break step for use cases where the + * original pte is not needed. + */ +static void clear_flush(struct mm_struct *mm, + unsigned long addr, + pte_t *ptep, + unsigned long pgsize, + unsigned long ncontig) +{ + struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); + unsigned long i, saddr = addr; + + for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) + ptep_clear(mm, addr, ptep); + + flush_tlb_range(&vma, saddr, addr); +} + +void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte, unsigned long sz) +{ + size_t pgsize; + int i; + int ncontig; + + ncontig = arch_contpte_get_num_contig(ptep, sz, &pgsize); + + if (!pte_present(pte)) { + for (i = 0; i < ncontig; i++, ptep++, addr += pgsize) + set_pte_at(mm, addr, ptep, pte); + return; + } + + if (!pte_cont(pte)) { + set_pte_at(mm, addr, ptep, pte); + return; + } + + clear_flush(mm, addr, ptep, pgsize, ncontig); + + set_contptes(mm, addr, ptep, pte, ncontig, pgsize); +}