| Message ID | 20240326171045.410737-3-willy@infradead.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Various page->flags cleanups | expand |
The fix for this particular file looks good,
but some other architectures still use page->flags
to test/set PG_arch_1 aliases:
./arch/arc/include/asm/cacheflush.h:#define PG_dc_clean PG_arch_1
./arch/arm/include/asm/cacheflush.h:#define PG_dcache_clean PG_arch_1
./arch/arm64/include/asm/cacheflush.h:#define PG_dcache_clean PG_arch_1
(in arch): grep -rI . -e 'page->flags'
./s390/include/asm/hugetlb.h: clear_bit(PG_arch_1, &page->flags);
./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags);
./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags);
./s390/kernel/uv.c: set_bit(PG_arch_1, &page->flags);
./s390/kernel/uv.c: if (!test_bit(PG_arch_1, &page->flags))
./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags);
./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags);
./s390/mm/gmap.c: set_bit(PG_arch_1, &page->flags);
./s390/mm/hugetlbpage.c: if (!test_and_set_bit(PG_arch_1, &page->flags))
./sh/include/asm/hugetlb.h: clear_bit(PG_dcache_clean, &page->flags);
./sh/mm/cache-sh4.c: test_bit(PG_dcache_clean, &page->flags) &&
... (not an exhaustive list) ...
But at least for xtensa, this LGTM.
Reviewed-by: Svetly Todorov <svetly.todorov@memverge.com>
Svetly
On Thu, Mar 28, 2024 at 12:36:30PM -0700, Svetly Todorov wrote: > The fix for this particular file looks good, > but some other architectures still use page->flags > to test/set PG_arch_1 aliases: > > ./arch/arc/include/asm/cacheflush.h:#define PG_dc_clean PG_arch_1 > ./arch/arm/include/asm/cacheflush.h:#define PG_dcache_clean PG_arch_1 > ./arch/arm64/include/asm/cacheflush.h:#define PG_dcache_clean PG_arch_1 > > (in arch): grep -rI . -e 'page->flags' > > ./s390/include/asm/hugetlb.h: clear_bit(PG_arch_1, &page->flags); > ./s390/mm/hugetlbpage.c: if (!test_and_set_bit(PG_arch_1, &page->flags)) > ./sh/include/asm/hugetlb.h: clear_bit(PG_dcache_clean, &page->flags); > ./sh/mm/cache-sh4.c: test_bit(PG_dcache_clean, &page->flags) && Fixed elsewhere in this patch series. > ./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags); > ./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags); > ./s390/kernel/uv.c: set_bit(PG_arch_1, &page->flags); > ./s390/kernel/uv.c: if (!test_bit(PG_arch_1, &page->flags)) > ./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags); > ./s390/kernel/uv.c: clear_bit(PG_arch_1, &page->flags); > ./s390/mm/gmap.c: set_bit(PG_arch_1, &page->flags); > > ... (not an exhaustive list) ... s390 is a disaster area for use of page->flags. I've sent patches with no response or "we can't do that" responses. I'm ignoring them until I get more useful responses. > But at least for xtensa, this LGTM. > > Reviewed-by: Svetly Todorov <svetly.todorov@memverge.com> Thanks.
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 7ec66a79f472..23be0e7516ce 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -87,12 +87,13 @@ static inline void *coherent_kvaddr(struct page *page, unsigned long base, void clear_user_highpage(struct page *page, unsigned long vaddr) { + struct folio *folio = page_folio(page); unsigned long paddr; void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr); preempt_disable(); kmap_invalidate_coherent(page, vaddr); - set_bit(PG_arch_1, &page->flags); + set_bit(PG_arch_1, folio_flags(folio, 0)); clear_page_alias(kvaddr, paddr); preempt_enable(); } @@ -101,6 +102,7 @@ EXPORT_SYMBOL(clear_user_highpage); void copy_user_highpage(struct page *dst, struct page *src, unsigned long vaddr, struct vm_area_struct *vma) { + struct folio *folio = page_folio(dst); unsigned long dst_paddr, src_paddr; void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr, &dst_paddr); @@ -109,7 +111,7 @@ void copy_user_highpage(struct page *dst, struct page *src, preempt_disable(); kmap_invalidate_coherent(dst, vaddr); - set_bit(PG_arch_1, &dst->flags); + set_bit(PG_arch_1, folio_flags(folio, 0)); copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr); preempt_enable(); }
Since switching to the new page table range API, we disregard the PG_arch_1 (aka dcache dirty) flag on tail pages, and only pay attention to it on the folio. Fix these two missed spots where we were setting it on arbitrary pages. Reported-by: Svetly Todorov <svetly.todorov@memverge.com> Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org> --- arch/xtensa/mm/cache.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)