From patchwork Sun Apr 21 18:01:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 13637453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0417C4345F for ; Sun, 21 Apr 2024 18:09:14 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 5973C6B00B1; Sun, 21 Apr 2024 14:09:14 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 547636B00B2; Sun, 21 Apr 2024 14:09:14 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 399D76B00B3; Sun, 21 Apr 2024 14:09:14 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 1E0526B00B1 for ; Sun, 21 Apr 2024 14:09:14 -0400 (EDT) Received: from smtpin13.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id CAEF5A137E for ; Sun, 21 Apr 2024 18:09:13 +0000 (UTC) X-FDA: 82034325786.13.20841E4 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50]) by imf15.hostedemail.com (Postfix) with ESMTP id D7685A0012 for ; Sun, 21 Apr 2024 18:09:10 +0000 (UTC) Authentication-Results: imf15.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=nLjc85bm; arc=pass ("microsoft.com:s=arcselector9901:i=1"); spf=pass (imf15.hostedemail.com: domain of Michael.Roth@amd.com designates 40.107.220.50 as permitted sender) smtp.mailfrom=Michael.Roth@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1713722951; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=mUcwiyFHOOyR1TxaHBGwT/R8u08BH+n1ydQXmt0BUDo=; b=N//Ylxkq1N/D96S+BrWky1DpFzoblB0HEiPtMFXW02FI3dCWFwJ8uVAggF3gptpwrZXxX7 RsIvpuj+m845aIO6qF8tuMwCtcvCVLVBOWtlkaSStIvRMpm92OZ3QyEAd6lILVjE2vogg0 NT46XszZ5suGLMjoAYIKvyRYp1ICdCg= ARC-Authentication-Results: i=2; imf15.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b=nLjc85bm; arc=pass ("microsoft.com:s=arcselector9901:i=1"); spf=pass (imf15.hostedemail.com: domain of Michael.Roth@amd.com designates 40.107.220.50 as permitted sender) smtp.mailfrom=Michael.Roth@amd.com; dmarc=pass (policy=quarantine) header.from=amd.com ARC-Seal: i=2; s=arc-20220608; d=hostedemail.com; t=1713722951; a=rsa-sha256; cv=pass; b=ljTX1NiV7ALynjDR33OnqFFBqgpUtrhhRvTQeDrF5chRLCysaBIRxqNOuUHevjy3kZqeKQ CUG4fRoT46tNIswVn0lbP2h2c41YEYQT+j540zYE8LcJbfw7WZGnNPbysVvL/vOZmb+hJa KSLu1pHwP6gRjRUhrV+QcHXJG3HEXaw= ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GhTe5uq0el5Ao6VZyd18+tbbXC5IVMDSuCKTOuGuUE+VFFy6CinTW6rOYBqsOEnWPDnf7CcKUZbq28b0wVVxx4Eh1/AdJk8CWarMMb2/ZFTvMHhJAkfEOd6Z+tE2iQhkrZJVGgX9Ec5t+5QPL59Obd9/LZGdkyh8Euduh3r+1uIKjZJQ+rK/UpiS/T/bAGxLJUkU8kAPxpY5/auFcLjV5b1k/u3ilVitlzW6wg4YtMZcm2Q4GUIMl8J0YyQSr8mK1fFOYkUgS+pH4fbGO7x3y8A/qeFOzJVrPxqNvW+wKSVRizelJbIO06KnBZezzBUi5GIyUDznbf8LCGfgF4WYeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mUcwiyFHOOyR1TxaHBGwT/R8u08BH+n1ydQXmt0BUDo=; b=UD8V9GBwoE04GYRd7YZQ0YI4AVyftlEsmbz1G0z9Axszdc7TROobl6ErRfftmNvc1KTvyPHl8dHEtFokQeHygHc4ZY59WOgPlKdJDvpWE0CfHlo97o1xAnhx9zlNdWoNyPUN6cofILh+PGKMR2nEMIh/hHdLZOPzStUZ9gLHOvaTcTXkE8JPO4D8FJ8rGLvq630nsH0j68X/BEXHPeeRpIW6Dz8cNyk5DfqIZ2yWwV2i0sFTVN3e1sPZxQwC+tpbfAjDaGHXb/WSZQEOoVsvK5e52VLdalR4YDmNUKwoRqdQ80tZJB+/WI2nTK+ECyjYzLgM2Aw8zJE1JUfLE7SJmg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mUcwiyFHOOyR1TxaHBGwT/R8u08BH+n1ydQXmt0BUDo=; b=nLjc85bmeMpHY4+KmPiz1lSmKf5c3iGwtbhjaOCa1ZeHxPklaTmVD8BByuNP6/RzHwGAA838g9SSQN6KUlHoYmaALQMIVR+Kv4IstiGxzJta9u36646ByjECHLgOAElTI15osR/CSVJh8C6ZHSztFR4VENXjLfbc+6WvjeQMU7Y= Received: from BYAPR11CA0097.namprd11.prod.outlook.com (2603:10b6:a03:f4::38) by PH8PR12MB7448.namprd12.prod.outlook.com (2603:10b6:510:214::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Sun, 21 Apr 2024 18:09:03 +0000 Received: from CY4PEPF0000FCC4.namprd03.prod.outlook.com (2603:10b6:a03:f4:cafe::68) by BYAPR11CA0097.outlook.office365.com (2603:10b6:a03:f4::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7495.32 via Frontend Transport; Sun, 21 Apr 2024 18:09:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCC4.mail.protection.outlook.com (10.167.242.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.19 via Frontend Transport; Sun, 21 Apr 2024 18:09:03 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Sun, 21 Apr 2024 13:09:02 -0500 From: Michael Roth To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Brijesh Singh Subject: [PATCH v14 02/22] KVM: SEV: Add support to handle AP reset MSR protocol Date: Sun, 21 Apr 2024 13:01:02 -0500 Message-ID: <20240421180122.1650812-3-michael.roth@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240421180122.1650812-1-michael.roth@amd.com> References: <20240421180122.1650812-1-michael.roth@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC4:EE_|PH8PR12MB7448:EE_ X-MS-Office365-Filtering-Correlation-Id: fc9b7ceb-3d34-4834-4b05-08dc622e20b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: huaABAK0E6/58H8ZcUROohLzz652unpG7GsDtz3fKe1GK/gXuqVQ7p2y0MttRBYj+WLS/ftxC2RzSd9Yz9DRWfRK3OvsUKu8b3zkVvBzMutUDBPAv8WmOODrgUrcu9JZQ/b/aRWdcL+Ud+0IPLU9aSOadWlPySp8h4KjN/Rboicfqis3Dg/Q23UcDk8bUwSUEQI1qyWOeN13JZtEkHOA4iv+KJevJPn1cVQ/wNmy5VEdOKyP27UXOoO6lO6mvNxAH/S5VOtMF8egrCY6DkJ6OTs92TbwjEWL1juhO0hPHWrifs40gfXmhSyMSr1bNtQ3pa3O7QsTZ7pEuaF1j7X4nS3JGlN8w6AO9hdzISw3COG57HHeQsD3BH+sZ3gXbf+ermmqi7kOZ9RAch/HORr2KQdgsDbAZzHMjYQSc9faN7AbSbqDyTx4E0O5+QHoY5NwtgYlTmJozQM5zd3O9KrFsVJtyHL2DE1gX27W8OT9rlV9eqswPDtZvxGRdB4yWl+WiYsPqFFX/bcbQADr+4yfpRir18sl2EiJ3vk1SqP3trfWIcn+nS2XcEpS8Ym5QKP6x9Ln7JNIkt0DziUi2xpa+aPFqLQhxNh/NP1l2557/7UgqlL/gl7hKsiRVjs9NLAYpHwFGMtvDJSWSJPUEEp28QaxJ44vldiKHuwjepeyWuHmIydwRNasNGgMh5gou5ZrwuIQYVeXAww5nNGqlcQhBvvZR/z56h1XPhStBhJeQiqUcLIbca6lCDZMjH1eMztCcpjBPR6GVbxZ2HZC/pIJJt6vQqo1DzxoR5BrhqMIEhlvPcwtHF3zZcAP8UccwfwAMsdrqn+JQ+/1JJx5vVWqbMf2f2jFDoETcqZt7EW5nzuW6cCVuwGJguhUEkcEFFjjSn9LcWmXgsnKc02xJj7k6asNVPFlxmsNvMzBeIsXwGNURvqIw8lXuHh6hucjWZpuZkHwu2X0P/M1OSyHg/lwPVZ2umY2l22AM/ri1F8+Uj6Bw0sysSdm9pBnWROj9k/CXgHi7zL/MwZY+/4OMh9nPm6ldfgyaQn4xZRJ60DnaV1OMkjkxSFZTSZ4FXXPTuBtwA8Co5cVEjUYbmdmvr+xr1nRSBheAt9/lAkuHt430GRUrUG7oAQtfFcK3f4LxelFImvcLuJH/ptm9tZSOuHpAegBRFgeiENzbQSpCzD2KazSu8so0uMuY9BzcRzlj0JhtQ94wRyXmBoHczUIWOQbJzZB44OGnleErZ+JxKgDdReh3u5xTLvZ3NOn6AZb+U1Q3CdhUS3RKRQEhOTdBPXe59OouCfCtrToTQhXnslpn/jYjODTGsOs6Plk60x75p8i4kC/SlHYiwVOM43BhmV81p972EiOcumU2suFn3GbuKkwSxIOZkL9UZbT4Vw7gJyh X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(7416005)(376005)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2024 18:09:03.5600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc9b7ceb-3d34-4834-4b05-08dc622e20b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7448 X-Stat-Signature: afdahsqdffoxmxiyr8jrrz3enxttdiwy X-Rspamd-Queue-Id: D7685A0012 X-Rspamd-Server: rspam10 X-Rspam-User: X-HE-Tag: 1713722950-554001 X-HE-Meta: U2FsdGVkX19C0py9b2RF8/kEP/g8szQDlE0p6h1s6linryyrygqDpQsrudpGu6BMnDaVxvFkK1NmRrW+aagMrexerRU21ML2NLxadp8BDV+XX4GLkHHR6zeh3yH7Uh4URpjAHfDs+IIT5Wj6ubSABpENdbRkFZfT7SaOxRuDL/UDbcbKdDD4mQhs0cEvZGntD/i9wiwQoJxpdW2+8NanEhGViOFHE+2Y1/VSSuGIwHW7kX9l8xnEKps4oXZtQf6KAHbKfDUXnfQEOLlOR+DUv+0kKayoADXPQGpTbJDZ6p394M1ou4oxux85XagWrjEGgDCbwWyslJakNGjtnU+CrgRaLRH8eneePBMy336OTACHgXgOz3+e4WMrNAgybw8X+M5PAljUgfaV7EnMuA+h4qntguj3MEnimDGefwPjtazOYgPwd9ro0ZRMgodTtLTOzfvBGIjUsYimUzrQumi/97sJDixlL4+7lDTa/hMfA5WjjpKbWdcV5S//8q30osFQPNf8TiFqTc6mdqd6ld0kDrZCJY3d/YIbaCPMpYLGSWvyvVPa8+uwgkJbIDHOR3Gi1dKUzmeZvyQwCTBQFGGQgEx6GtcK7/uBHcJdHVSRDnVhoQyZXIWMmPtOLBFlYkSABdEG6sfgN9Ix3atlegIHIFh+7TQDyDeQ7OsA+D+f4UJQJJBrSwbo/QwUkXJul5na6soHoB4dgHfsrSgPmb5Ligcvc/t43/vBZA0gdzZRx4h2d4AKwjspgBp3x6gSCzy/MlRQyLxqebfUNBJhmIqkgJDqMZk5UZ0Hn9ctJ1DzkQWoelmvWu4lkNT0QQoktf1E7BlXtMaXyqAXZlWFh8vD7nQ8oFnThgWZvLwnbArzucF3cLvhp7XvwiovkTo026ah8ANrqrD4BiMP0ZRxODEodEJIydxOdjphnvY9CfON0GBhp3VsF9yVXzenmCCRfxna0i3QFVPc9lK5wWtOPT+ 1kXx/ETm Ao1YMhR8vj/Vyjlxct7JAgsYIbSHHVWnYV4lsVxugA9CkeR4cfS9yeQKlPAhHgjz3gRAByY1YfSlmW7xAe6jXXIXz/pIuMMv0DAjmR/0H48ZiQ0rf+R3BNn3EhkGFKavALbLQsokziYDkbjjzcnfK87qEwOSU4HaBqjppfZy/p1Tgak1CwLx0ANH39gdRJmuD2ZGt13rDcFdvFC+9iT4KOufqTfkki1Zzt5cXDcSCrwUSCePzlaUQREqZfzX1gTNWcjNrier47OrCAPf8KgRPUHeDff3q33PSky38xh/Z7xkOMoIxYVNEKg/eei3uU//Klc/tSdNwA8Bv82k= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Tom Lendacky Add support for AP Reset Hold being invoked using the GHCB MSR protocol, available in version 2 of the GHCB specification. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra Signed-off-by: Michael Roth --- arch/x86/include/asm/sev-common.h | 6 ++-- arch/x86/kvm/svm/sev.c | 56 ++++++++++++++++++++++++++----- arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index b463fcbd4b90..01261f7054ad 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -54,8 +54,10 @@ (((unsigned long)fn) << 32)) /* AP Reset Hold */ -#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 -#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) /* GHCB GPA Register */ #define GHCB_MSR_REG_GPA_REQ 0x012 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 598d78b4107f..6e31cb408dd8 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -49,6 +49,10 @@ static bool sev_es_debug_swap_enabled = true; module_param_named(debug_swap, sev_es_debug_swap_enabled, bool, 0444); static u64 sev_supported_vmsa_features; +#define AP_RESET_HOLD_NONE 0 +#define AP_RESET_HOLD_NAE_EVENT 1 +#define AP_RESET_HOLD_MSR_PROTO 2 + static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -2727,6 +2731,9 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) void sev_es_unmap_ghcb(struct vcpu_svm *svm) { + /* Clear any indication that the vCPU is in a type of AP Reset Hold */ + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_NONE; + if (!svm->sev_es.ghcb) return; @@ -2938,6 +2945,22 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_AP_RESET_HOLD_REQ: + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_MSR_PROTO; + ret = kvm_emulate_ap_reset_hold(&svm->vcpu); + + /* + * Preset the result to a non-SIPI return and then only set + * the result to non-zero when delivering a SIPI. + */ + set_ghcb_msr_bits(svm, 0, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); + + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; @@ -3037,6 +3060,7 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ret = 1; break; case SVM_VMGEXIT_AP_HLT_LOOP: + svm->sev_es.ap_reset_hold_type = AP_RESET_HOLD_NAE_EVENT; ret = kvm_emulate_ap_reset_hold(vcpu); break; case SVM_VMGEXIT_AP_JUMP_TABLE: { @@ -3280,15 +3304,31 @@ void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) return; } - /* - * Subsequent SIPI: Return from an AP Reset Hold VMGEXIT, where - * the guest will set the CS and RIP. Set SW_EXIT_INFO_2 to a - * non-zero value. - */ - if (!svm->sev_es.ghcb) - return; + /* Subsequent SIPI */ + switch (svm->sev_es.ap_reset_hold_type) { + case AP_RESET_HOLD_NAE_EVENT: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set SW_EXIT_INFO_2 to a non-zero value. + */ + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, 1); + break; + case AP_RESET_HOLD_MSR_PROTO: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set GHCB data field to a non-zero value. + */ + set_ghcb_msr_bits(svm, 1, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); - ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, 1); + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; + default: + break; + } } struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 323901782547..6fd0f5862681 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -199,6 +199,7 @@ struct vcpu_sev_es_state { u8 valid_bitmap[16]; struct kvm_host_map ghcb_map; bool received_first_sipi; + unsigned int ap_reset_hold_type; /* SEV-ES scratch area support */ u64 sw_scratch;