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Fri, 3 May 2024 06:02:25 -0700 (PDT) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: akpm@linux-foundation.org, aneesh.kumar@kernel.org, aneesh.kumar@linux.ibm.com, bp@alien8.de, broonie@kernel.org, catalin.marinas@arm.com, christophe.leroy@csgroup.eu, dave.hansen@linux.intel.com, hpa@zytor.com, joey.gouly@arm.com, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, maz@kernel.org, mingo@redhat.com, mpe@ellerman.id.au, naveen.n.rao@linux.ibm.com, npiggin@gmail.com, oliver.upton@linux.dev, shuah@kernel.org, szabolcs.nagy@arm.com, tglx@linutronix.de, will@kernel.org, x86@kernel.org, kvmarm@lists.linux.dev Subject: [PATCH v4 10/29] arm64: enable the Permission Overlay Extension for EL0 Date: Fri, 3 May 2024 14:01:28 +0100 Message-Id: <20240503130147.1154804-11-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503130147.1154804-1-joey.gouly@arm.com> References: <20240503130147.1154804-1-joey.gouly@arm.com> MIME-Version: 1.0 X-Stat-Signature: hemcygzfioz5ajsnfhk7y56gun5atfkq X-Rspamd-Queue-Id: 3D3241C0012 X-Rspamd-Server: rspam10 X-Rspam-User: X-HE-Tag: 1714741349-619453 X-HE-Meta: U2FsdGVkX18/NpkSLb+ixzh6Sm7egSvKH03G6d1wCWBqEMWQzDz1TeZmmVMKKc7z33lJWhYnrcZMXgrgOsmiBXRkdvgm3Qo6OMdLOld1EN675q93+MVEVh1fBtN9/e+Mj0aShu5TldQjN/K4myNDL6ParUkCE1C+8Hz9GBUzHQLGAIZHyJ794aJNX0dl5xp3LMlxn7a/FpL06ioVxVWPgwc/CNlciqWhGz91oA9/LDx1lPrWNvwqBwZF2BCpJbglXl6KSCaSwTPL+2FHwHxU7ykvnUcs6rii7TmhWcmMb3GYsuw7mZv8I39vrxHimzIsk6h8zLIT35DpPMVtchYoWC6O/h37SfbwpBR+rPDeo7GMjDJt0SUrMXMuJRlVdfBs4SwmnWZv4TqgdWetZWFwKn+8nwkriKlP+vYr9xiaAz0nuGQgSa2MxjZNjsaIkIKdxI4hVHYyVuwt1gNR14xEDFkRla6npy0IDTCWS2dZfrnx1a+Td8GpY2lzNfDh3XRtDLVQWvgyNW3tvh6DHIgTk0J//aJbF8lgv7ZhvkwVSt4j6WT4Aw7By4dK4GXDNQ4QbxZC8HQoohtgLZ2NMcgal54XTjmEebUt9K0Vr5maPBx2zdjpqvRfY3PP6AAc4Pk/ElkjJB+HDZAnpvhvy3F1NIR81KHYbiFoiRj35/3sR9vxkmMkcdfFfwVT5IZGdn51Xw2ZLhSseH0I+S8Jv9BXFagxBcjj5UdN6eR631BK0pWReJEOhvMBSuAOwvBkNb+AvHzEqCNn+O9yxaS1ZkPgKqI9YSScv2K0ibej0c8QYjWchRGx/XRKg676N4TpZja6z574lywgo5G+BcLpgiZrMqgE+9bU07gAvw3Mo57DxjLP8KAc3vnVuN1+8Rl5ChxbpX8cFIS2RQHsuqD8xzjmzcbWe2y5+2YMLWJrtVfKCiuCYORfILz6lhCx9U5vhLa9UQZh62h+BvTtgO3gRq4 +UFZ2gso Yqx1WoLYUHABgNNyhGz2Ns14oNctAVQJxV7Qlriwi/YoKcd/pDNY4U7lFyovnAmthFgxuLlrr8KWnwT3QDl70icsQUuG6lmblAhrpKqpE0Ns766Oq7d+tGG8JYNBDmw2XPAfMvc3ZZaa/GDSFnK+oOyEUOzQuEQL6PblchtaWD9NDsSN7Sg5TGU6pwtdJNj4Iz3+H/clEgOaiWw6+aEmeOQIuPyHCUF6JiBphOuoc3I8MdcuqKP0kNYXmc2VriHEId1wiT7xX1TNK1i8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to check if the CPU supports the feature. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: Catalin Marinas Reviewed-by: Anshuman Khandual --- This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 19 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 448c1664879b..694f67fa07d1 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 HWCAP2_SME_SF8DP4 Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. +HWCAP2_POE + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 4edd3b61df11..a775adddecf2 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -157,6 +157,7 @@ #define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) #define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) #define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) +#define KERNEL_HWCAP_POE __khwcap2_feature(POE) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 285610e626f5..055381b2c615 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -122,5 +122,6 @@ #define HWCAP2_SME_SF8FMA (1UL << 60) #define HWCAP2_SME_SF8DP4 (1UL << 61) #define HWCAP2_SME_SF8DP2 (1UL << 62) +#define HWCAP2_POE (1UL << 63) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2f3c2346e156..8c02aae9db11 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -465,6 +465,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), + FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), ARM64_FTR_END, @@ -2339,6 +2341,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); } +#ifdef CONFIG_ARM64_POE +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); +} +#endif + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2867,6 +2877,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_HAS_S1POE, .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_poe, ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif @@ -3034,6 +3045,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), +#ifdef CONFIG_ARM64_POE + HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), +#endif {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 09eeaa24d456..b9db812082b3 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -143,6 +143,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", + [KERNEL_HWCAP_POE] = "poe", }; #ifdef CONFIG_COMPAT