| Message ID | 20240503130147.1154804-5-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Permission Overlay Extension | expand |
On 5/3/24 18:31, Joey Gouly wrote: > Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > --- > arch/arm64/include/asm/el2_setup.h | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index b7afaa026842..df5614be4b70 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -184,12 +184,20 @@ > .Lset_pie_fgt_\@: > mrs_s x1, SYS_ID_AA64MMFR3_EL1 > ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 > - cbz x1, .Lset_fgt_\@ > + cbz x1, .Lset_poe_fgt_\@ > > /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ > orr x0, x0, #HFGxTR_EL2_nPIR_EL1 > orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 > > +.Lset_poe_fgt_\@: > + mrs_s x1, SYS_ID_AA64MMFR3_EL1 > + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 > + cbz x1, .Lset_fgt_\@ > + > + /* Disable trapping of POR_EL0 */ > + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 > + > .Lset_fgt_\@: > msr_s SYS_HFGRTR_EL2, x0 > msr_s SYS_HFGWTR_EL2, x0 Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Hi, On Fri, May 03, 2024 at 02:01:22PM +0100, Joey Gouly wrote: > Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > --- > arch/arm64/include/asm/el2_setup.h | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index b7afaa026842..df5614be4b70 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -184,12 +184,20 @@ > .Lset_pie_fgt_\@: > mrs_s x1, SYS_ID_AA64MMFR3_EL1 > ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 > - cbz x1, .Lset_fgt_\@ > + cbz x1, .Lset_poe_fgt_\@ > > /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ > orr x0, x0, #HFGxTR_EL2_nPIR_EL1 > orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 > > +.Lset_poe_fgt_\@: > + mrs_s x1, SYS_ID_AA64MMFR3_EL1 > + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 > + cbz x1, .Lset_fgt_\@ > + > + /* Disable trapping of POR_EL0 */ > + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 Do I understand correctly that this is just to allow the host to access its own POR_EL0, before (or unless) KVM starts up? KVM always overrides all the EL2 trap controls while running a guest, right? We don't want this bit still set when running in a guest just because KVM doesn't know about POE yet. (Hopefully this follows naturally from the way the KVM code works, but my KVM-fu is a bit rusty.) Also, what about POR_EL1? Do we have to reset that to something sane (and so untrap it here), or it is sufficient if we never turn on POE support in the host, via TCR2_EL1.POE? [...] Cheers ---Dave
On Thu, Jul 25, 2024 at 04:44:13PM +0100, Dave Martin wrote: > Hi, > > On Fri, May 03, 2024 at 02:01:22PM +0100, Joey Gouly wrote: > > Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2. > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > --- > > arch/arm64/include/asm/el2_setup.h | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > > index b7afaa026842..df5614be4b70 100644 > > --- a/arch/arm64/include/asm/el2_setup.h > > +++ b/arch/arm64/include/asm/el2_setup.h > > @@ -184,12 +184,20 @@ > > .Lset_pie_fgt_\@: > > mrs_s x1, SYS_ID_AA64MMFR3_EL1 > > ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 > > - cbz x1, .Lset_fgt_\@ > > + cbz x1, .Lset_poe_fgt_\@ > > > > /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ > > orr x0, x0, #HFGxTR_EL2_nPIR_EL1 > > orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 > > > > +.Lset_poe_fgt_\@: > > + mrs_s x1, SYS_ID_AA64MMFR3_EL1 > > + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 > > + cbz x1, .Lset_fgt_\@ > > + > > + /* Disable trapping of POR_EL0 */ > > + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 > > Do I understand correctly that this is just to allow the host to access > its own POR_EL0, before (or unless) KVM starts up? Yup. > > KVM always overrides all the EL2 trap controls while running a guest, > right? We don't want this bit still set when running in a guest just > because KVM doesn't know about POE yet. KVM currently unconditionally traps POE regs currently, this series makes that conditional. > > (Hopefully this follows naturally from the way the KVM code works, but > my KVM-fu is a bit rusty.) > > Also, what about POR_EL1? Do we have to reset that to something sane > (and so untrap it here), or it is sufficient if we never turn on POE > support in the host, via TCR2_EL1.POE? Since the host isn't using it, we don't need to reset it. It will be reset to an unknown value for guests. In patch 7: + { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1 }, > > [...] > > Cheers > ---Dave Thanks, Joey
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b7afaa026842..df5614be4b70 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -184,12 +184,20 @@ .Lset_pie_fgt_\@: mrs_s x1, SYS_ID_AA64MMFR3_EL1 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 - cbz x1, .Lset_fgt_\@ + cbz x1, .Lset_poe_fgt_\@ /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ orr x0, x0, #HFGxTR_EL2_nPIR_EL1 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 +.Lset_poe_fgt_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 + cbz x1, .Lset_fgt_\@ + + /* Disable trapping of POR_EL0 */ + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 + .Lset_fgt_\@: msr_s SYS_HFGRTR_EL2, x0 msr_s SYS_HFGWTR_EL2, x0