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Thu, 12 Sep 2024 16:17:27 -0700 (PDT) From: Deepak Gupta To: paul.walmsley@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh@kernel.org, krzk+dt@kernel.org, oleg@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, kees@kernel.org, Liam.Howlett@oracle.com, vbabka@suse.cz, lorenzo.stoakes@oracle.com, shuah@kernel.org, brauner@kernel.org, samuel.holland@sifive.com, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, greentime.hu@sifive.com, charlie@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, xiao.w.wang@intel.com, ajones@ventanamicro.com, anup@brainfault.org, mchitale@ventanamicro.com, atishp@rivosinc.com, sameo@rivosinc.com, bjorn@rivosinc.com, alexghiti@rivosinc.com, david@redhat.com, libang.li@antgroup.com, jszhang@kernel.org, leobras@redhat.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, costa.shul@redhat.com, bhe@redhat.com, zong.li@sifive.com, puranjay@kernel.org, namcaov@gmail.com, antonb@tenstorrent.com, sorear@fastmail.com, quic_bjorande@quicinc.com, ancientmodern4@gmail.com, ben.dooks@codethink.co.uk, quic_zhonhan@quicinc.com, cuiyunhui@bytedance.com, yang.lee@linux.alibaba.com, ke.zhao@shingroup.cn, sunilvl@ventanamicro.com, tanzhasanwork@gmail.com, schwab@suse.de, dawei.li@shingroup.cn, rppt@kernel.org, willy@infradead.org, usama.anjum@collabora.com, osalvador@suse.de, ryan.roberts@arm.com, andrii@kernel.org, alx@kernel.org, catalin.marinas@arm.com, broonie@kernel.org, revest@chromium.org, bgray@linux.ibm.com, deller@gmx.de, zev@bewilderbeest.net, Conor Dooley Subject: [PATCH v4 05/30] riscv: Call riscv_user_isa_enable() only on the boot hart Date: Thu, 12 Sep 2024 16:16:24 -0700 Message-ID: <20240912231650.3740732-6-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240912231650.3740732-1-debug@rivosinc.com> References: <20240912231650.3740732-1-debug@rivosinc.com> MIME-Version: 1.0 X-Stat-Signature: i1b85dimda17m4x65a4tmhppu6ccgxck X-Rspamd-Queue-Id: 51F564000D X-Rspam-User: X-Rspamd-Server: rspam10 X-HE-Tag: 1726183049-276695 X-HE-Meta: U2FsdGVkX1+YC8jRAkFOczZ0VH1OSAMgU8Lv20txaY5ik7YUEF714jU3dGllVWr7Bre1ZZ3QveVLsbt4fe7k96CJqdWg78pqsY2cDKjqN30H+e6V8BG5nvn1TODLdo78oKzFlt9TpTlhzvMFH92k//HLkTaUG5JAcM7kPJOZZQim792vZho4Gh3/w9dvW8b7gA5m6HWQQf7mYOhe3UovApGsW/ZY/YiUbOdJq4n7zUlQsnUFy9d50nadoY6Uw+XefAZkvYT8i4kotF0/FZ/pj3rulHp9+3i0ciE5gcS/HaxlXf+GLM4TsRU0HoqEdWlW9Bo4MPVirLgrNMCJG6bJa1FroM1wSJOAKkKpVOt/ytLIv6Fref1zY45q6VwRitThMNmLoWM1Kvc6vDwVQAxptVq37elmQMjkXeendYoYRiNKkJbNa8BsukEF5I5J3lV2IPqTa8mDKL96RHi8Ewr0C+BqSgvXtAYOIDekR5CVcfFw4P574uZkZgR9JEjNRNRuUCOm3zptd2t3ju1Gajp+txvRwL+pB6yzo/WcqPsFZE44Un8LZrUsFU2uBL4nMxFHQcg6yRNUsPFY3dh27vj3bEiHohpNOPNmShx3O8P21mm0rxYmOWFnN6tnwWdBFrdUFYvVp9Nhwqc92KRfcjKiyXLFtrPHw15urgrGWN5AbzVFab94ChB71GERC+P41BGUUdZJ8Ay5LCnYUj6LThm9hcofXoY4m7mCu6zgx77GKf3EwzFvOyTplZGDsJeAV6lQNQi2eh5EZSCeBnsP5pCIrdOTRQoRSuFGZ8TBw+2RkkhVEJilsJXThRU3t0JZohy4Zgg51kdtqUvKdSqM8YQbY8BYxYz92SKgLMPMFWZ0e7Uyga7f8H1IjN7auAr/aQNHb7zwhtilJ/jK3qPZkYRr3NupUlb/eqZ03xlubE29UzBwFh3w3cDZWbvDgu+krPfnKSPRqgnacnLKhRp9u1h grgpA27M IQzw18YPnjstZWaSttScii/eZzmlnEJdoLzVucDbnKEAsV9twhslKn+ZieVj8n25OL2j92NWJbrEulsTHFX/F/wrGT3qKz7gIRerSy4BXd6OvGPexdqui+JTWWnPTW6IScj0Vr5MKnEfQhMF5zt4vyUblnVR9yXoaqPgIJhrO3LkbTLwROcYG76TKoyfZ8FgGGB7INr0+OvK2Z5CfRz6iYJgqXn/XPZK0/Hf7PxbP09q4yFdzIcu83yaRlcucIEz1EbVcHwUKUHDZKpKwnySti8YjInQlBwMgRutwNGd1ri5328sUPO0ncwBP+yNuxzk97qE52bNyVpjdtp4X1RBkt8krthLyMSMwslPl1Vfu4PdxZKE+9cO07NJVL1+2u+6VxSVHD9WeRxpNjX6JTAWAqvfkpkpsLJx5w6XSM6xx6D0qmJvAUOkaTKu0dRzdzcarG+wH+WaAzpqAcgxWzTnt1QLG8B8I7Vshju0rODAjZoSFWft8tFB+DsvLroaeds2GiTT59g8BIFklyejzXkHI6ArL82NKcrbbrZQGegSW0r0QO6ySLByUH8tejZRRa6hWH9yZdoJNcfc1Zhn3a0LLufrD8YkWbWUe9TCxwSv9AG2vqlHQ+5rzhqWfw5Mn4vT4BJFgmZJx71tu0uZy6HLrTLsGJfOVBEwtD7pEIemKiTGUL5o= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Samuel Holland Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Deepak Gupta Signed-off-by: Samuel Holland Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 4 ++-- arch/riscv/kernel/smpboot.c | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 45f9c1171a48..ce9a995730c1 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; -void riscv_user_isa_enable(void); +void __init riscv_user_isa_enable(void); #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \ .name = #_name, \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f7fcd23d55de..41fd0be25bd8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -919,12 +919,12 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } -void riscv_user_isa_enable(void) +void __init riscv_user_isa_enable(void) { if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) current->thread_info.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) - pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); + pr_warn("Zicboz disabled as it is unavailable on some harts\n"); } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0f8f1c95ac38..e36d20205bd7 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, true); - riscv_user_isa_enable(); - /* * Remote cache and TLB flushes are ignored while the CPU is offline, * so flush them both right now just in case.