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Tue, 08 Oct 2024 15:38:00 -0700 (PDT) From: Deepak Gupta Date: Tue, 08 Oct 2024 15:36:47 -0700 Subject: [PATCH v6 05/33] riscv: Call riscv_user_isa_enable() only on the boot hart MIME-Version: 1.0 Message-Id: <20241008-v5_user_cfi_series-v6-5-60d9fe073f37@rivosinc.com> References: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> In-Reply-To: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta , Samuel Holland , Andrew Jones , Conor Dooley X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Queue-Id: 87013A0006 X-Rspamd-Server: rspam01 X-Stat-Signature: syij98zni971efp5fu8797xb9odjiduf X-HE-Tag: 1728427082-467061 X-HE-Meta: U2FsdGVkX19osH740vf9ibrJ+xcuCJOYDOFlpBi/FNOKkQm9WD+ovuprBTTVWk+d5yDvQg+xcn7vvRpQXFQbo3xbFFvn91NQL8mmNCdaUaoKnqxdy/8O9BDgEocZqcY5BbIsaAf0H4KMIwzXtu+HclENKguJHTNWSe1ZJkE2kJGCw/fTtBJ1mr0Hs97lOcDyyXtLl4gneZcSPmFjh0/ZtEMXRaons7FWT67k/3RditxxvL3I8hHww9lLB2Mj+63U9N8IIu/AXtT6NgglTDkwdq1LSs0yqddVet0xo80ZXjWBNBzUwd9ZwXpc2l5Z1rJobqFRVYhAAncKwBZdSshFI/A7xvm6jYfRstzfHDhHvv1ISAlbx4AGoXV+QBfQtnrIagC2Ml64HMHagW/82qMk0UrNVX4LQo2ax+SVu2qFrjokaya5wtqYhr/kQsHjsVTe2Uw8tog4AKinSCLCWk3HzPlqAgqgOF1E9LWF4ipUHAAVx34h9cUishegMmNjPXR8cZp6EwFPTW3xSF1IOrbarEBl/LOgBWkOf+BHxAeKenKCSOqpfxtPiIEZ5sd/dOLxVHqouUhHunTKFVRMewSKac1zTaVF01/ZJonAjzcPnaaqwG9zkhjb24cboDkARiM3oPpadTlVqe3w3FcyLRAkp1Nz+Nsz21NCAEs70Llcvn6wln4PLlt8AH/JWmHmWqkEWqGA9/lCTiv4Ax/4RJv7M+N63gaOPPXX4QojOjLON4P9cZxejwTlaEThymooozpUtDq8SYFrjPV8p3LnJBXS27vtrx06742BNYMnep6qERCQwiqhh3HW/PUMPjOOC8BvlJHaKW3HNTXEA/bVuqfsfgosPKxRRPkoOpJgPc4o1qN9CXVA/eE00seRY824kBpPmfGfLhdqRE55Zlt7RPA3QIb/8jcsnIZbzagigDFmgaqL4N91f0BS54xNO/7Ivt9WFBQDo/E3XvlVaoi2H8j ZltVe3Mn 4Nh6VMIO4iVHV8t1UZw+5goU3w1Rvb5aRLVEKeQFNfu0OVMwEBfHWToxrp5aYQ3vsGTy7pdJmpBLfBVfTRf9kgk8uHbC8ipM0TFN3vtJG+VhEG6L0GZX+nivR/kEzYwBKcrkR8VzbdUMJezZix5l+y2184Z6Zv/1I7SMXD0EDF7LD/XBXiqYLHyhyBBqu6xROodurrzkPVdKRliki/9OLAZLF4a5UhypQKIhaCsWn4wx+MH6w5NVLozNvxEWNR1/i8vxuS7i7YeZb7Nb8sXu3+PLP3F5pgME8UtOdIaNqnX0s/yySCq/CJnRmV1ql/f0l1BEG4h0EIKhkBk0b37YvWbm1tnZv3gjAdgbjx0A3W0CafYQUhb3zhcx1nxE7xVB3Qez9cnzP/Dx/pbvtLDRaFnhvn5z0dBcRf2rzR7nxNDaf6PJsay8wuRBkJnZBmCEVnhL5trFjf2qeGAczaWUIB5WqhnT7tLxA8IHFrsdqOV9Ek33VqTkqxGOt+fs28MsMQORkOvsErc7hiTROsEtliJ7kUUOMj0nN/rSUG7B09WnGlN4AncAn6hlkCndL7FXXprcs9F/w0QCN6MaW4nMaqugo/ylluryUeJ0h/N3d0Ps+zz5sEPHnymPfRMXSZLrWSh4SLVQUQp+0sP4nMHX1hZ1T512HB6yizPofAzmhaII7DsdvoPeHeQVqaQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Samuel Holland Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Deepak Gupta Signed-off-by: Samuel Holland --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 4 ++-- arch/riscv/kernel/smpboot.c | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 45f9c1171a48..ce9a995730c1 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; -void riscv_user_isa_enable(void); +void __init riscv_user_isa_enable(void); #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \ .name = #_name, \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 27bafc5dd62d..b3a057c36996 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -920,12 +920,12 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } -void riscv_user_isa_enable(void) +void __init riscv_user_isa_enable(void) { if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) - pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); + pr_warn("Zicboz disabled as it is unavailable on some harts\n"); } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0f8f1c95ac38..e36d20205bd7 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, true); - riscv_user_isa_enable(); - /* * Remote cache and TLB flushes are ignored while the CPU is offline, * so flush them both right now just in case.