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Tue, 29 Oct 2024 16:45:32 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Oct 2024 16:44:29 -0700 Subject: [PATCH v7 29/32] riscv: create a config for shadow stack and landing pad instr support MIME-Version: 1.0 Message-Id: <20241029-v5_user_cfi_series-v7-29-2727ce9936cb@rivosinc.com> References: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> In-Reply-To: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Queue-Id: ED32916001F X-Rspamd-Server: rspam01 X-Stat-Signature: txerwbpo3khsi5u5jpsw63itbnqkptmr X-HE-Tag: 1730245516-523543 X-HE-Meta: U2FsdGVkX19L5SuDaSHKQYQmR7r1FjDLmC2iWvB8N5gny/u25k/t+sPuQDO6UCCp8vQAJhUHmb5VDhfdjVf2622OqVUgn+jMBrERiZuKpFZzvWc2f4nYGpa7jt4zSMkPyDnBee95iH5L6d8yI43mPkGS0aiGwWbbqtGDolplQjnX2p0sPL6ayjT3bXESeiHt/OiPaiACF1N4kPq0vx0rgAThU0xPIIrRy7hJr5qwqDo8FXwADTM42BiwlGGVq5YjT4UwVi4YgOZNoX5ZS7h2390tGnkQkcNaX2rI0N38ttIp4niucCDjCkbTtGBxamR0qUYxSDavdthq1YmFxLq3xImFxVgk18+bxrM4/ZynFN7pMoRDf891Zuz6ICz5RFxg2apzWbhc/L9C4aSIgu8V3Kjb/5thwdH4EwD9eGVDo1rDDyn0/sAeslTshe+LV4WNMhYYDkap6k3OoilDbMr7uGy++2qeLKJD44mE+U3mPxWGVLmS2SvDxAH0ngftYlc/mW9qz0tBVHdFr/7jxwCRh29t7U1UEwPQR6odKV0AgzHv4/RpLimwG7d2zgIpVw5ld+hUs1/fOSCKb/StouKOm15T2N7C53BGY4pab48B6nOLwunLFJn1vDI7N1G/icCwC+ufaGAYJhMUssWTK9YZi7yplJG/dCjVMw4DSEtiLecrzFGUg2gc3LE60eXeCnxlqdMkVtJuyXtDt4d/yH3btkxHz5OYf20oZuxkLULY1ktwJtnQ7x/HM4/sYjsCRwB9iQbT1YYkZ7M77P2MtsNMpBKKwbnxj4aJ4nRjNBBj6apg1/ikyfM9TSOU1Kyvz+0hqMkXn4P3wzUdlGd0uYtETmU6gUaPEPnaZpCAXKQdj8EHSg/xNtAEjA7YeysK3omwrq6glgC1diytubjxm5x8hzsRvSikvoFtco1LWPW+7qJPD/BM52g4LgrNt9hDyRC7l775hRSJZs/PszJIrS4 FhInAMVf v1aMvZfzkz9aI64zvuNOjceV/TD//kGi6esi7NfYke29GKCiC1LYfel1YBi2KXH/3W1y+kwcnysM6kf3q5t7L64teKnkOFRaCKareCZISf4SEuwt3V8m3LbR6yVwFsx9RrdfW25HUEBjeMmSq3HGvt6IgrwmsagNi1Z8wlSxXHj0al/kXNIjGVruGA26FnaYO7PgmBNe2PnYsvtRPVIHw1Etdxnd5mWa+uE0Qu4cl2LaEDtBk1pjhajEtQi6QXZHpXOoroh1QMHXxtMhGdTN0qiBCEThpbE76kNmy3rJ2ob9Y+umDSIv8h+jqd1PArSDyEKPHs2Q+ZypSeLXetqJYelElZWuDjqY2vw/rHpcgwE/rvGLr6Pe1yUYOBxFG9mv/dG6G/B5CwBN0fkE4C39wcTMoUx2RnG34OjXzPbce3Qdkk/+snk4ZGOuHkfKgG2UaQVWRSdffL8ziQ/qS2b1gVEpLcyRhwjcS2sNThhojvkR6kYE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi. If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv. Signed-off-by: Deepak Gupta --- arch/riscv/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 22dc5ea4196c..53f367609c70 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -244,6 +244,26 @@ config ARCH_HAS_BROKEN_DWARF5 # https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77 depends on LD_IS_LLD && LLD_VERSION < 180000 +config RISCV_USER_CFI + def_bool y + bool "riscv userspace control flow integrity" + depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss) + depends on RISCV_ALTERNATIVE + select ARCH_HAS_USER_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + select DYNAMIC_SIGFRAME + help + Provides CPU assisted control flow integrity to userspace tasks. + Control flow integrity is provided by implementing shadow stack for + backward edge and indirect branch tracking for forward edge in program. + Shadow stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Indirect branch tracking enforces that all indirect branches must land + on a landing pad instruction else CPU will fault. This mitigates against + JOP / COP attacks. Applications must be enabled to use it, and old user- + space does not get protection "for free". + default y + config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT default 8