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Tue, 29 Oct 2024 16:44:33 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Oct 2024 16:44:07 -0700 Subject: [PATCH v7 07/32] riscv: zicfiss / zicfilp enumeration MIME-Version: 1.0 Message-Id: <20241029-v5_user_cfi_series-v7-7-2727ce9936cb@rivosinc.com> References: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> In-Reply-To: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 2A3BD100004 X-Stat-Signature: utekbrzchnxsa4xx1sewqqekxbhoig4f X-Rspam-User: X-HE-Tag: 1730245446-953909 X-HE-Meta: U2FsdGVkX1/Gx6XNpg7rVZKZI4NpxTUPTiP9IQgmRPGXnxXkhyN1HAtaYDPSNJUyry5qIv1EFdDec/YybTl+tG1yzDul+nc2uMjUf40W98bZTmJ7kd+uDjRwx0xE+COhUOEyElEfqBk+++e1SWHIcbCNqrPbQadH/9lf9l797eBQZFnT7UPcz33s1i83KgEgTARGmhYwz0p0wmdFwjeuaJq1R9XV5OrRjGyKDshsojAkOtQBmUC++3on7JVojsxKbbqslCvC2cheMYWCoHy6KanFUaDXUFjyqErmRnq+giHaXOqcgF5MiYjkalKF16dVAMCk5w61G+2qTdhgBxxnhV0BDZ6oxeKR9rjRHniIbWNNWPiDwACrKZsP3Js2Bbt1RrK2QwryfOhjEsHcMeO0G/WYuyaM6P04/qn5+rqXlKCXACYr+6Hq5C4IPXe1ym1AC4+d6pQpO+tSbRpvZMqMNwah+iIStIBCGzc7/ozAaIrZ7tOsAGOAsqimVPPLknzKMFA9XoZPsDhuvV2lS6+L8q9FCXbp4mwjEW7/nCvC8NhurwjTfHCTIBF23ialjYEm7TdrQ40dpnXE0iPJuMiiJsrtyFuYSm1pi2fVtnp44eB7pYArBf5NDnd7X0Dgq9G2IrxmJGAPCE0PFg5Xq1w/y1EITpaJAXXnB9vFGYtIuTqiACIJnfwm7WIt6tUDcuEuYAqZlR4510fPcjCIgMFaPIvRlS9ZbaikQVwGnik1bJ/wSdO9Ygh3mpogQcrWDEUI067EjFJ8QZ6qcTHra29G3oOFzI+xNPpI4zLFpWYJO5HzircsFnt4zB+GduKuQYQbG+cXm6THXe+CYckJLK7+CxtrTOMomPR7r7TO83OCjVX87N+OY/JW0xgdTt7OiF95d/zmPH+Kj5+Wffw4Zz3eqO0OP3JEoCj2JvbDrm3a5Tq7QSoD6RHaLIDREhL5x7XJMow+Uxa9TexfgKHgmJL 2oaqQ6yy 1FKB4bFg0+AbnuiZhZ5RRBMHf5Y+gWXF6QcmAxzR+iZA27eQZNEMvWSBqAs9e2q4c5NNtNUFAr2+MDY/c2mBRcAkW/AtESxQ921jdWHoHpndC5YkyJ7QCQno9effPV1QMC7r+L9bp2AgM0g1TA9cWgUbLsIY26ESnMtQL4D7GbP0/flP4jrO5nZ7jPiPYickc2R1tG9YcIS8ZKRFRz90jipoI4yFY+0UYZLYGUd7/IjmIdNs1cn7M/C/qvhQTcvzrZMaSOpN+mzKbrgxyQG6eGnv/rrtoJCA1ajZMz0Hlc3+CqDIC30kytrdRUAfUznjllfLofk4JlW46NXxm5e3cGOStcGc+pTzGN6vjzdcGxc+A+4/pYgVIa1FdmdKzPAZnYx1e27UabzAYSMp0czzV9YXpmewylvX/ONjp9v1z3KVT3bKkQXo6NDamZQvLmBvl8PX3RfnY+pdth8bfoXgI5X44kvlyuY5BOrQ6tO2go23Bh9aOlUJiBAsEWQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ 4 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index ce9a995730c1..344b8e8cd3e8 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -180,4 +181,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 46d9de54179e..10d315a6ef0e 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -93,6 +93,8 @@ #define RISCV_ISA_EXT_ZCMOP 84 #define RISCV_ISA_EXT_ZAWRS 85 #define RISCV_ISA_EXT_SVVPTC 86 +#define RISCV_ISA_EXT_ZICFILP 87 +#define RISCV_ISA_EXT_ZICFISS 88 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index c1a492508835..aec3466a389c 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,6 +13,7 @@ #include #include +#include #define arch_get_mmap_end(addr, len, flags) \ ({ \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3a057c36996..70803aa66332 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -317,6 +317,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { riscv_ext_zicbom_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),