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b=ro+xITsNu5F26//ZeVzOlDOKW2NFRJ4ZIIuT8QdesLC6GZdb8OBPw1G+EgDMjJsvpGkrcA IxNG4RmVoXTV6zgMIeVJdDy8fworOH9rKlOea+BWE/trbtCXh7bCOMb2CPAZM7gxFatNqL MfqeSEMmgPB9dNq8OgN68K2VMe//+Ms= ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf02.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740099325; a=rsa-sha256; cv=none; b=REJai8cxj7mytcTrMQfodj5daRxHyJwNsZlhULRphVXoQDHpj7HImJ3RQOXsRjYSt1C2Vd Un5za2lEUDof8BtuYb6s6spiNgTI86si9jS2HldtjIwNJm4eU2XQd+IOSnB134xO0OtYHu zqz/Dz+WO80FCa+trQOIuquiTBEOvrQ= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tlHIZ-000000003Qf-1Okl; Thu, 20 Feb 2025 19:53:47 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, Rik van Riel Subject: [PATCH v12 09/16] x86/mm: global ASID allocation helper functions Date: Thu, 20 Feb 2025 19:53:08 -0500 Message-ID: <20250221005345.2156760-10-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250221005345.2156760-1-riel@surriel.com> References: <20250221005345.2156760-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 4C8238000A X-Stat-Signature: ui5j8jh4cccwfkcmy39di4aijpd3ik8x X-HE-Tag: 1740099325-721273 X-HE-Meta: U2FsdGVkX1+vdKS3RgqRA75POv7B+4ICNHw67AOJB4kpb6o/P7Cua64FWpqmciJjutEi3qpiSj48L7Sn5/f7E0iuYoDWtyxu0bu6IydHpeP6qGbkoH0GR3nkMgnklpdwgDCoFVhcR74XGKofHGPm4jZg20V1c/q71reOZ/kW6hCTfkyaXp/W5mrzPExO45Eeie3ggLf5qZCujC+P3FRPhqHbJ3w+pZZ9OKzKL+pGRMpFD4goKobWKnmiQiAAQQavIDnTiDUnwvMlPpYTMXG6OMi3DwhpoK5I2ksnkd6ARXQIW65FTO891ZyvCkbvWaQSFKkxCne2MI9nK8f/YOA6tDWNJmCXxnGXs52SVUGbhc8l/XCCONVT9Gdp4VDT/kNLsszx+vGbRoYl8BXwh8s2u2QGEiY5JYe5SQ6G/GWKKRZyWi8VG3+t3VanjAyE00vWqLJxbpLMhpOA+TWxuJ8AS3w11L03Vga3ZAWI1WgdtkVWO9ktOqpJLtoaiqHolrIYZKANNLbVU+GGPpoHG9jmu00r/StPZc2SSg5bde8E78wio1kq6b1Ci1neL3yV1rMfe38HW/XtKas8U8grZ2ZCujgvP00s2cZ1oES0l2JCaX1ABZt8jC0OntEH3nlgiXJTpsOhWh0k93qrqNvgTswlZaiyOYs9is9T+Y4egFsWNBSISEaDbc1tsuIjpGc7MTJA1ZkHdt0OSYtaUgqfH1kpLHRxX7T+VhRzVClaSrarKUgKADZB1JnbdMnx1buoo7LdLsnbszrB6dmXZ+Q0fOuPlLrNr8AFExvmyXtOPI1fgei01ElUKelxjipZ9hVOgyTjALaTpXTXWC9XBJ5yuMvTqvt+RL2oHRC09sm/OwxF+91Y+nfkmZBnurZs0IX28se9ZQuUOs1LLew7OItZ1FL+CmKwImQ1zY8KvA0XWDTCq9R6/fNro2g5FNgyzX8vWaCV5mw8i60LgpTN6DJ292+ 65Eq30PP +BvtftFDjPXsSoe3Of1evZVRiXfA9IISFx3RrmM4kl5c3gMu+W4sTf03gBx4+50kkdgxdqxRl4SLhJ8VqepQ0SoJ8j5zntFJpGep73lsYxSi0eO3miDYQ30UBl951Gb8yRXKF6qJfrC7xQLl7SNJ/o8VQv2toefdjkw2RTMzSFGpbM2HW8e0RFTyAcXJJx5PoAuW96ZCWsar6rlbdzBbIuI9T58yunPJcYgAV0moge1ldPrnEB4KDKxkI+9B9AfKdRAq3SKym8gbFG5NxKWrdaMOgVO/bWMRRkAgVQgacmUlu9QZmt9FJP2EGgkZopcB1WCCX3lzf07QmxFFUoaPAx4aITr2b09xIyI/Xa4zU2wKySL2aKRycV9Deukm6sovEor9stR4HVi0h91aKeLgHiES2C2v82qyAThl6SYplkAmmLDDLedRSFhgqLAJEM/S1xJCM8GSirDO+7MT+bDQ3hPvtnf5tfWUWUWPOfq41V4xLhPM= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Functions to manage global ASID space. Multithreaded processes that are simultaneously active on 4 or more CPUs can get a global ASID, resulting in the same PCID being used for that process on every CPU. This in turn will allow the kernel to use hardware-assisted TLB flushing through AMD INVLPGB or Intel RAR for these processes. Helper functions split out by request. Signed-off-by: Rik van Riel Reviewed-by: Nadav Amit Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley --- arch/x86/include/asm/mmu.h | 11 +++ arch/x86/include/asm/tlbflush.h | 43 ++++++++++ arch/x86/mm/tlb.c | 144 +++++++++++++++++++++++++++++++- 3 files changed, 195 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 3b496cdcb74b..edb5942d4829 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -69,6 +69,17 @@ typedef struct { u16 pkey_allocation_map; s16 execute_only_pkey; #endif + +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + /* + * The global ASID will be a non-zero value when the process has + * the same ASID across all CPUs, allowing it to make use of + * hardware-assisted remote TLB invalidation like AMD INVLPGB. + */ + u16 global_asid; + /* The process is transitioning to a new global ASID number. */ + bool asid_transition; +#endif } mm_context_t; #define INIT_MM_CONTEXT(mm) \ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 09463a2fb05f..83f1da2f1e4a 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -234,6 +235,48 @@ void flush_tlb_one_kernel(unsigned long addr); void flush_tlb_multi(const struct cpumask *cpumask, const struct flush_tlb_info *info); +static inline bool is_dyn_asid(u16 asid) +{ + return asid < TLB_NR_DYN_ASIDS; +} + +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +static inline u16 mm_global_asid(struct mm_struct *mm) +{ + u16 asid; + + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return 0; + + asid = smp_load_acquire(&mm->context.global_asid); + + /* mm->context.global_asid is either 0, or a global ASID */ + VM_WARN_ON_ONCE(asid && is_dyn_asid(asid)); + + return asid; +} + +static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) +{ + /* + * Notably flush_tlb_mm_range() -> broadcast_tlb_flush() -> + * finish_asid_transition() needs to observe asid_transition = true + * once it observes global_asid. + */ + mm->context.asid_transition = true; + smp_store_release(&mm->context.global_asid, asid); +} +#else +static inline u16 mm_global_asid(struct mm_struct *mm) +{ + return 0; +} + +static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) +{ +} +#endif + #ifdef CONFIG_PARAVIRT #include #endif diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 16839651f67f..405630479b90 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -74,13 +74,15 @@ * use different names for each of them: * * ASID - [0, TLB_NR_DYN_ASIDS-1] - * the canonical identifier for an mm + * the canonical identifier for an mm, dynamically allocated on each CPU + * [TLB_NR_DYN_ASIDS, MAX_ASID_AVAILABLE-1] + * the canonical, global identifier for an mm, identical across all CPUs * - * kPCID - [1, TLB_NR_DYN_ASIDS] + * kPCID - [1, MAX_ASID_AVAILABLE] * the value we write into the PCID part of CR3; corresponds to the * ASID+1, because PCID 0 is special. * - * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] + * uPCID - [2048 + 1, 2048 + MAX_ASID_AVAILABLE] * for KPTI each mm has two address spaces and thus needs two * PCID values, but we can still do with a single ASID denomination * for each mm. Corresponds to kPCID + 2048. @@ -251,6 +253,142 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, *need_flush = true; } +/* + * Global ASIDs are allocated for multi-threaded processes that are + * active on multiple CPUs simultaneously, giving each of those + * processes the same PCIDs on every CPU, for use with hardware-assisted + * TLB shootdown on remote CPUs, like AMD INVLPGB or Intel RAR. + * + * These global ASIDs are held for the lifetime of the process. + */ +static DEFINE_RAW_SPINLOCK(global_asid_lock); +static u16 last_global_asid = MAX_ASID_AVAILABLE; +static DECLARE_BITMAP(global_asid_used, MAX_ASID_AVAILABLE); +static DECLARE_BITMAP(global_asid_freed, MAX_ASID_AVAILABLE); +static int global_asid_available = MAX_ASID_AVAILABLE - TLB_NR_DYN_ASIDS - 1; + +/* + * When the search for a free ASID in the global ASID space reaches + * MAX_ASID_AVAILABLE, a global TLB flush guarantees that previously + * freed global ASIDs are safe to re-use. + * + * This way the global flush only needs to happen at ASID rollover + * time, and not at ASID allocation time. + */ +static void reset_global_asid_space(void) +{ + lockdep_assert_held(&global_asid_lock); + + invlpgb_flush_all_nonglobals(); + + /* + * The TLB flush above makes it safe to re-use the previously + * freed global ASIDs. + */ + bitmap_andnot(global_asid_used, global_asid_used, + global_asid_freed, MAX_ASID_AVAILABLE); + bitmap_clear(global_asid_freed, 0, MAX_ASID_AVAILABLE); + + /* Restart the search from the start of global ASID space. */ + last_global_asid = TLB_NR_DYN_ASIDS; +} + +static u16 allocate_global_asid(void) +{ + u16 asid; + + lockdep_assert_held(&global_asid_lock); + + /* The previous allocation hit the edge of available address space */ + if (last_global_asid >= MAX_ASID_AVAILABLE - 1) + reset_global_asid_space(); + + asid = find_next_zero_bit(global_asid_used, MAX_ASID_AVAILABLE, last_global_asid); + + if (asid >= MAX_ASID_AVAILABLE) { + /* This should never happen. */ + VM_WARN_ONCE(1, "Unable to allocate global ASID despite %d available\n", + global_asid_available); + return 0; + } + + /* Claim this global ASID. */ + __set_bit(asid, global_asid_used); + last_global_asid = asid; + global_asid_available--; + return asid; +} + +/* + * Check whether a process is currently active on more than "threshold" CPUs. + * This is a cheap estimation on whether or not it may make sense to assign + * a global ASID to this process, and use broadcast TLB invalidation. + */ +static bool mm_active_cpus_exceeds(struct mm_struct *mm, int threshold) +{ + int count = 0; + int cpu; + + /* This quick check should eliminate most single threaded programs. */ + if (cpumask_weight(mm_cpumask(mm)) <= threshold) + return false; + + /* Slower check to make sure. */ + for_each_cpu(cpu, mm_cpumask(mm)) { + /* Skip the CPUs that aren't really running this process. */ + if (per_cpu(cpu_tlbstate.loaded_mm, cpu) != mm) + continue; + + if (per_cpu(cpu_tlbstate_shared.is_lazy, cpu)) + continue; + + if (++count > threshold) + return true; + } + return false; +} + +/* + * Assign a global ASID to the current process, protecting against + * races between multiple threads in the process. + */ +static void use_global_asid(struct mm_struct *mm) +{ + u16 asid; + + guard(raw_spinlock_irqsave)(&global_asid_lock); + + /* This process is already using broadcast TLB invalidation. */ + if (mm_global_asid(mm)) + return; + + /* The last global ASID was consumed while waiting for the lock. */ + if (!global_asid_available) { + VM_WARN_ONCE(1, "Ran out of global ASIDs\n"); + return; + } + + asid = allocate_global_asid(); + if (!asid) + return; + + assign_mm_global_asid(mm, asid); +} + +void destroy_context_free_global_asid(struct mm_struct *mm) +{ + if (!mm_global_asid(mm)) + return; + + guard(raw_spinlock_irqsave)(&global_asid_lock); + + /* The global ASID can be re-used only after flush at wrap-around. */ + __set_bit(mm->context.global_asid, global_asid_freed); + + mm->context.global_asid = 0; + global_asid_available++; +} + /* * Given an ASID, flush the corresponding user ASID. We can delay this * until the next time we switch to it.