From patchwork Fri Feb 21 00:53:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13984683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB44C021B2 for ; Fri, 21 Feb 2025 00:55:32 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 7AF3A28000F; Thu, 20 Feb 2025 19:55:24 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 6EBB328000B; Thu, 20 Feb 2025 19:55:24 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 4CE6728000F; Thu, 20 Feb 2025 19:55:24 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 26FFD28000B for ; Thu, 20 Feb 2025 19:55:24 -0500 (EST) Received: from smtpin22.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id D7146120259 for ; Fri, 21 Feb 2025 00:55:23 +0000 (UTC) X-FDA: 83142133326.22.3F56729 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf15.hostedemail.com (Postfix) with ESMTP id 54A88A0008 for ; Fri, 21 Feb 2025 00:55:22 +0000 (UTC) Authentication-Results: imf15.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf15.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1740099322; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LdvwmofdFF3hDY0t7ucFzvQKImtHH2rUisVGBSrpDs4=; b=wrkBislADukh9A4rGxhmA6rtjswXMA1snY0JJ0QE5wrhpr4X92DZumTJiiIlz9df9RGC5a vOTU98vb7Ndh+xNM3N+xzmaF9Jj31kSh20vchO/BfTf+tCfhrd5FY6xXkPBl2iwlEuNJ88 dC+JqNeZYZcFtTlpYSw20JXx5xStQGc= ARC-Authentication-Results: i=1; imf15.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf15.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740099322; a=rsa-sha256; cv=none; b=TO0nJYF7EnJUdhgaZ78kP5uX3dyW0EveGlJxdihzMUJWEvZv0WaZwHVc51E94UUjPhMkYU 0+RZ/Dj4u4FkjoLUm1Zl0MuVKOOTk2GlA8trnhNGcxR+uRKVLIf1fX+6pzgY/QW3KGb7Pd sUv/LL3DocDnrMS5OPlNk9WSzj8e9fc= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tlHIZ-000000003Qf-1rzG; Thu, 20 Feb 2025 19:53:47 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, Rik van Riel Subject: [PATCH v12 13/16] x86/mm: do targeted broadcast flushing from tlbbatch code Date: Thu, 20 Feb 2025 19:53:12 -0500 Message-ID: <20250221005345.2156760-14-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250221005345.2156760-1-riel@surriel.com> References: <20250221005345.2156760-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Stat-Signature: qdhqtft4wh9hygwu3k5u8d94wnpbpgs8 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 54A88A0008 X-HE-Tag: 1740099322-110206 X-HE-Meta: U2FsdGVkX1++PvCeALTOGY2K3fCgzQ6AnnwC4oXMsRQt+AR3xoeGOi/Ba6X30XxW/tTz7S4zKgmQapFoRxDnNcLQZ4N2oopHllytON0YELQj2OTim162IMmhNTqCwu4v+2i3ZXDx6X/TWQ/ud1/lE76SXWvtejglWOGRf0i/bxnp+0pPCqXQkQ7WmLtN18HaDu360YAKkvGr1+PG1th+vtn0ehlnCWRGUGgKUIR7fljzK96ZU0tmLEl6b53LMS2t7RYGh4p8+mi/xNIlC1M05SfabFC2hfxxk9Jv1gU6seDeN4m85W4HUhenPUgPp044i8ToV8zg8QZ8MxGoUO/B+gJL2bdpbn7172KDV6ozVEL9xwokiSPwkQc+LJGWZujUxTnc1/2NT9Xbn2WHqhMdn4IXsVQXCyos+peghYTjfGP/BNjQiSiHDfT3V+eTY37Cd36vsaUi8VytbFASvg4devI/YJmIPx0LAe7qfWgiEZXcvG5uBTFnpCTUPPUT1Y3x6MTbh7n/yXKcg/H2fyUyijcPKqX/gdbgUuoIkG1Qmi2f694Wuxwj9iTvM1rpY6GkLk12qfqolFV7m4oYuuSYqEfiptubzww/DOIMp62pwiTOw/aC3ajugx8YxhV32Ruwf8MmWcS/9XOC8kaTU67/1cEV2f0LPLvfK+1Lq2WDWYJEE7iqtxPghCXPwomMNikGlN2LGrJXHgiQ2yIVvIVOysIyURSYuGlE31yvtQxj7RkC/3667LKDbLwlVVI9SSWcAQPvhCz/TXhnHFE52GYH/ueXTLmPRiBiA+jyl3UHeeftCbrmnLDw3stWrPi/Cf27ZYQRUr3iDKuCeubJ4RpxVXsLr+PRsUMOUtDmZVHZ28K5Pqr9UOat4a5Qq3oFzc7ni8zMWt2qNbDr+y3p9GrahdoEkb3G3YKp83dTvKcWQvCxE+62ug8qebNYlCglxrkQqbTTMv0oe2GfE84IPMC fmcczH7p VkTchbqCi3uzxC2WgFYjpK/4Shs4dqQdoi2F/1+/IEQrvPn6W0mEKxzfgSZPdZ4CVOeOzn/fHx5l8LW6xwI0w9gSUC0J07bkJDQ5iqcYMsXbA/QsitcwchgI5IxEOuF/DDKa4Vi/Rglh809FKwZSgSJLgNCQqKi1qx/5NZAO8ahs5tejHdup6JJayW2DCZUPcz+nY5uGqyDZB69J7ZtjXO3IWYhH32009lU8iTB19EeUqDdJF3eGeKjGitS/7hKsOMlgVjnQVGP9ZfNAVdkOXZnwuxacqU8rCFP+RmU+hGahIZ+uYm0CtVohZfBksGbpyHqOfYzvkx+KOhjdVoDdxWS6eTbLfb7g1IN6ZIuZ/Yg5v9TFQ0j52SCLwRiGwtE11ENw4iiER6Sf+vqInyw5q/dw7fUpXyNZAed3HSvXbLEyFN9/lC57Om41t+B3Iu2E5eNbzfumhf6cVl1k= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley --- arch/x86/include/asm/tlb.h | 12 ++--- arch/x86/include/asm/tlbflush.h | 19 ++++---- arch/x86/mm/tlb.c | 79 +++++++++++++++++++++++++++++++-- 3 files changed, 92 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h index b3cd521e5e2f..f69b243683e1 100644 --- a/arch/x86/include/asm/tlb.h +++ b/arch/x86/include/asm/tlb.h @@ -83,16 +83,16 @@ static inline void __tlbsync(void) #define INVLPGB_FINAL_ONLY BIT(4) #define INVLPGB_INCLUDE_NESTED BIT(5) -static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, - unsigned long addr, - u16 nr, - bool pmd_stride) +static inline void __invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) { __invlpgb(0, pcid, addr, nr, pmd_stride, INVLPGB_PCID | INVLPGB_VA); } /* Flush all mappings for a given PCID, not including globals. */ -static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +static inline void __invlpgb_flush_single_pcid_nosync(unsigned long pcid) { __invlpgb(0, pcid, 0, 1, 0, INVLPGB_PCID); } @@ -105,7 +105,7 @@ static inline void invlpgb_flush_all(void) } /* Flush addr, including globals, for all PCIDs. */ -static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +static inline void __invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) { __invlpgb(0, 0, addr, nr, 0, INVLPGB_INCLUDE_GLOBAL); } diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index f1f82571249b..241fa1435375 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -105,6 +105,9 @@ struct tlb_state { * need to be invalidated. */ bool invalidate_other; +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + bool need_tlbsync; +#endif #ifdef CONFIG_ADDRESS_MASKING /* @@ -288,6 +291,10 @@ static inline u16 mm_global_asid(struct mm_struct *mm) static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) { } + +static inline void tlbsync(void) +{ +} #endif #ifdef CONFIG_PARAVIRT @@ -337,21 +344,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 01a5edb51ebe..9ca22c504f82 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -485,6 +485,37 @@ static void finish_asid_transition(struct flush_tlb_info *info) WRITE_ONCE(mm->context.asid_transition, false); } +static inline void tlbsync(void) +{ + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + return; + __tlbsync(); + this_cpu_write(cpu_tlbstate.need_tlbsync, false); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, bool pmd_stride) +{ + __invlpgb_flush_user_nr_nosync(pcid, addr, nr, pmd_stride); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb_flush_single_pcid_nosync(pcid); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb_flush_addr_nosync(addr, nr); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + static void broadcast_tlb_flush(struct flush_tlb_info *info) { bool pmd = info->stride_shift == PMD_SHIFT; @@ -783,6 +814,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, if (IS_ENABLED(CONFIG_PROVE_LOCKING)) WARN_ON_ONCE(!irqs_disabled()); + tlbsync(); + /* * Verify that CR3 is what we think it is. This will catch * hypothetical buggy code that directly switches to swapper_pg_dir @@ -959,6 +992,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { + tlbsync(); + if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) return; @@ -1632,9 +1667,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1643,12 +1676,52 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + tlbsync(); + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + u16 asid = mm_global_asid(mm); + + if (asid) { + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (in_asid_transition(mm)) + asid = 0; + } + + if (!asid) { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or