From patchwork Sun Feb 23 19:49:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13987226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id F16DAC021B6 for ; Sun, 23 Feb 2025 19:51:26 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id B4B056B0095; Sun, 23 Feb 2025 14:51:16 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 7CAF86B009A; Sun, 23 Feb 2025 14:51:16 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3D6F86B0092; Sun, 23 Feb 2025 14:51:16 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id AD07D6B008C for ; Sun, 23 Feb 2025 14:51:15 -0500 (EST) Received: from smtpin28.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 4E0F1AFFDC for ; Sun, 23 Feb 2025 19:51:15 +0000 (UTC) X-FDA: 83152253310.28.F668BE4 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf03.hostedemail.com (Postfix) with ESMTP id B37B12000E for ; Sun, 23 Feb 2025 19:51:13 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf03.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1740340273; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LdvwmofdFF3hDY0t7ucFzvQKImtHH2rUisVGBSrpDs4=; b=vDGwLP+Nl6x+HAnBGo2gjP6nnl/8OQtdPi9SA7H/YaZL/ywleQetInUu7meoE2jI7uc+AI W5jK+MfUv/saaYGMmQ7qu03TqMOZMIgi4qPblu56osqfJ/hOxC7F1fWinWJtnUh6gZwD8K y+Y9TKWK/75lOQYhQYA3zIcjKTirO7k= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf03.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740340273; a=rsa-sha256; cv=none; b=HtV7fA17gk0iW/HR/Sy9FvuFsnyOIUQC7xAbtDCBAcejEFtCthPJKFA2Rzq6/HFnkDs6x/ b5zUtrzhJN6p2kmiP+54M7mt6ndLzZvAkc0biYlspFt17oC4TyiJ3ZYZFjOhOgb7sngp8i lMb3A38dYfeUMyRYHUbRv9isiJOnPQo= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tmHyz-000000001hX-0E6O; Sun, 23 Feb 2025 14:49:45 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org, Rik van Riel Subject: [PATCH v13 11/14] x86/mm: do targeted broadcast flushing from tlbbatch code Date: Sun, 23 Feb 2025 14:49:01 -0500 Message-ID: <20250223194943.3518952-12-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250223194943.3518952-1-riel@surriel.com> References: <20250223194943.3518952-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: B37B12000E X-Stat-Signature: p6jn6s5dc7jdq8xbcpj39kyzq9o8ymue X-HE-Tag: 1740340273-373754 X-HE-Meta: U2FsdGVkX185tHXjgR0qGxuVns6iqEnErTenKLDB99PYDwy3hIPPntZOcIxtJqwveLUD2uO2uCa+WbYZy1XMvg2knXU5bR1uHrNoZG6RAC4AQRVPbGj2jG0OJbtjfhFgN8TT++Is/eitq4o0RnKnGD5pwCwjU8UAGcUvSU7KzU9Px3TZkUCQXN/5LTvCD1gNa4a6bAR5fLVj8yFoWjlv8SCxdbmAiljC4XfIVqCuFKx8e2LI8S99zTyR0v4k5xiGSN3qEdBCwildecUwy7xj9D4tNo7+npo/rNwY0G/Odsi2MhFDuSfCMIf5bkBiIzycqUsS34z9tkPnJPR7S+yPK0p3x+3atsopTLtuy83V1ke81CncswZIy8+3WTXQiH5YiQQGw0eZ1n5ukLN6UnRpzxm0vjQkS/VaEiDdf+4jAkcvSAc7i3HM3bTBqca3Q/WFmDPd/fMv7EDnW5APc61BbyIQ/y9pOov4Y9rF3vy20XMRB1As0czBk3sxcT4p6e78R3zM7wjU8JVRyp8tDyvvqVz3EEuKxhXzEonbFVTa0xbhH7XwTKgjV0YUDalQjPdQMtPG9sHvXiHfRiJa4c7K/MakpTtOLkch5NXNBrs8HqVJD4neZiyKsNxp7ilmlXG2KlguoLy0EJqSGXJEncupy8nJs6NMHd6kJpD2vbStp+4LOC2Yiu60AQmlRTdYUPNFb99tVixiqXiW1OUasn07M6/fRVSrLsV2mp7hAY3ZRyvCIETE61rjbPepurUK/OddVl+m/zELcZqaPRYBP5OXCBWrJAsrxxEdwqXSMJv4rtuHeB4F+oFEtmgPavGiP2yR7OgRenSPJyRrGK0iIChNaRP+tewOvjU3sGsq4IZ7NUpEmzC9bnq88oZPAYEZ3PxJfV7Fdf6OoFdrRG6ea5PKIYN+ArtDXd5u7G5wVmAlYh+/NdCUh+X21/etAr4QAlcx9BVyHn8KfWJm9ip7g09 jOBC46H0 WbEHydvpd+DWEGzPrPQLiuu7BKw1lKBJZgpsrYPwqNwGksSbCUuokIYhipSil+s45uWxC875Wd5MN//uPu5tz/otV1+9u8Bsaj0J3LGE+30ILi5OkFQJTFwnPQvCUoTGdrV1inGezC52pfG8ku+eA8STBmfUOaBYlwDxhrk2eWOojw9X2xS+eoAsRUOWLqkszXX4kvXTZzjyMXDRDgzrPVvss3312u1dI97hHI4nuoWmn4LYHQQ52z/c6xdHApK44DrHQbCPa1CRYjz7MpjoyzrF3OXKRhGK0cPMgp/K0dJtBYoXUuox8w/TbrvbcfGlhQjt/4nABkzVDO5S7RbjjUfYYnM7mWUI06+lR6g2j3R248O4BSWqn4eb3cL8H7Dfq1rq2RH2fWVo+lsFiDXWlJ1afPkR63BZPdZgnlAfGdW3ffEepg17I1nrVB/dl7E/Bcv89MXn7wSyj/pk= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley --- arch/x86/include/asm/tlb.h | 12 ++--- arch/x86/include/asm/tlbflush.h | 19 ++++---- arch/x86/mm/tlb.c | 79 +++++++++++++++++++++++++++++++-- 3 files changed, 92 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h index b3cd521e5e2f..f69b243683e1 100644 --- a/arch/x86/include/asm/tlb.h +++ b/arch/x86/include/asm/tlb.h @@ -83,16 +83,16 @@ static inline void __tlbsync(void) #define INVLPGB_FINAL_ONLY BIT(4) #define INVLPGB_INCLUDE_NESTED BIT(5) -static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, - unsigned long addr, - u16 nr, - bool pmd_stride) +static inline void __invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) { __invlpgb(0, pcid, addr, nr, pmd_stride, INVLPGB_PCID | INVLPGB_VA); } /* Flush all mappings for a given PCID, not including globals. */ -static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +static inline void __invlpgb_flush_single_pcid_nosync(unsigned long pcid) { __invlpgb(0, pcid, 0, 1, 0, INVLPGB_PCID); } @@ -105,7 +105,7 @@ static inline void invlpgb_flush_all(void) } /* Flush addr, including globals, for all PCIDs. */ -static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +static inline void __invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) { __invlpgb(0, 0, addr, nr, 0, INVLPGB_INCLUDE_GLOBAL); } diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index f1f82571249b..241fa1435375 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -105,6 +105,9 @@ struct tlb_state { * need to be invalidated. */ bool invalidate_other; +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + bool need_tlbsync; +#endif #ifdef CONFIG_ADDRESS_MASKING /* @@ -288,6 +291,10 @@ static inline u16 mm_global_asid(struct mm_struct *mm) static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) { } + +static inline void tlbsync(void) +{ +} #endif #ifdef CONFIG_PARAVIRT @@ -337,21 +344,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 01a5edb51ebe..9ca22c504f82 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -485,6 +485,37 @@ static void finish_asid_transition(struct flush_tlb_info *info) WRITE_ONCE(mm->context.asid_transition, false); } +static inline void tlbsync(void) +{ + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + return; + __tlbsync(); + this_cpu_write(cpu_tlbstate.need_tlbsync, false); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, bool pmd_stride) +{ + __invlpgb_flush_user_nr_nosync(pcid, addr, nr, pmd_stride); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb_flush_single_pcid_nosync(pcid); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb_flush_addr_nosync(addr, nr); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + static void broadcast_tlb_flush(struct flush_tlb_info *info) { bool pmd = info->stride_shift == PMD_SHIFT; @@ -783,6 +814,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, if (IS_ENABLED(CONFIG_PROVE_LOCKING)) WARN_ON_ONCE(!irqs_disabled()); + tlbsync(); + /* * Verify that CR3 is what we think it is. This will catch * hypothetical buggy code that directly switches to swapper_pg_dir @@ -959,6 +992,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { + tlbsync(); + if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) return; @@ -1632,9 +1667,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1643,12 +1676,52 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + tlbsync(); + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + u16 asid = mm_global_asid(mm); + + if (asid) { + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (in_asid_transition(mm)) + asid = 0; + } + + if (!asid) { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or