From patchwork Sun Feb 23 19:49:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13987227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B87BC021B2 for ; Sun, 23 Feb 2025 19:51:29 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id E14D46B0083; Sun, 23 Feb 2025 14:51:16 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 9C47C6B007B; Sun, 23 Feb 2025 14:51:16 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3E2896B0095; Sun, 23 Feb 2025 14:51:16 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id E64376B007B for ; Sun, 23 Feb 2025 14:51:15 -0500 (EST) Received: from smtpin02.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id A2D238027E for ; Sun, 23 Feb 2025 19:51:15 +0000 (UTC) X-FDA: 83152253310.02.4A8EAEA Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf18.hostedemail.com (Postfix) with ESMTP id 115081C0015 for ; Sun, 23 Feb 2025 19:51:13 +0000 (UTC) Authentication-Results: imf18.hostedemail.com; dkim=none; spf=pass (imf18.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1740340274; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oh1XTOganrHAXrn6/YqDJlPae8gxQKo7DQ7P4yE2UVs=; b=R7bqJ+JaZFzpP7oJBYUG0Fgk9UI+djJOKSodx8TZsdW2cfXMbQATo7wo/zw/cL675s48M1 nUJoOi4ZbCeW1HYbGvsVSbIvcLXqZ0lXu7XkQUb7PSy5JCq5ikMGNYnxqWXBCZE/Mdfg1t dtXPuhm3sHLU/UpWLuMmj35Cp5FlOK0= ARC-Authentication-Results: i=1; imf18.hostedemail.com; dkim=none; spf=pass (imf18.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740340274; a=rsa-sha256; cv=none; b=XU3bu/1nYg16nObU0iSgUgOwGis7xCmB9l9OoFMIiI+UQzuSl1Q2AS9xFc6qezfNBeXSes NXpUcXqYyE+9WH40/fMt2T9KFW9qzEk0397XwipozaI5yFrc1mxr458idE8vfzJ18EWvM7 a+FfN/ZC+3IiSIjGQgdNkOiO+VLwAEc= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tmHyz-000000001hX-0Lxz; Sun, 23 Feb 2025 14:49:45 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org, Rik van Riel Subject: [PATCH v13 12/14] x86/mm: enable AMD translation cache extensions Date: Sun, 23 Feb 2025 14:49:02 -0500 Message-ID: <20250223194943.3518952-13-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250223194943.3518952-1-riel@surriel.com> References: <20250223194943.3518952-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 115081C0015 X-Stat-Signature: icmnsbgabbry1nxouhn1qpndqi4f16hs X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1740340273-190674 X-HE-Meta: U2FsdGVkX19oThujpZnpSE9urIK89xiPn2740EiMMknXbTMhqu74syMU7j86Xo8dxXkFGIL7mBuSObse6Tn17zNvUE1g43T573Y4teE/K7R6GyXJBGKewpVzm7j12/vizh9VrIGsEJ+bp6ThxNfykwX9WNBudfg1z/S6InLHgnIP+mfITI1Q0anUUdJsWm4/yrlQcayq6qo3EFNyAEEecasciH3PVVLkmeNW5hUa8pEST65eDg05YZ7X9iFFM3Or0VXkj3d2wEML9nFyEfH+1cx0P06v0jhi6gFOxDElrOPxnCdjvKMlvTxpIbWirzOuKptuML1G8/yZa41q0j+GUOFs4PJnOTLSNAOgY6cpY4MlW33thpL+6CUulnCdb360el8l3CxOZJhjoiPbhsaic9JGZmWp0BiB2IX19PNlMaRA9s+f2dDXYZ/J0ZGYZHKUaCIe07KCnT5/ZuN9CL8xeI9S1B2dYX47rKro49aE1P9N7BDpBPKFLjMjKoL2hwYs2R+craSKObcNsRnUtgSuBN5hOQcmsF4MDHbEAzzzduZz0i1nemDuIrfTmbxhLvXR/ZQ0nHWE74iBIXKz3B9APmcRIQQhrgMe2bruW8VRsDrohQXCW7sQdrL/tzeHg/SxTTyYR4AfLLB8Pd3gp3xhQfmLchBiSi0jyi63JJJh9ljedLm1H6JjlTuAgqmH1c1VndPunOzLQX7fU+jeV++OhymllcodTov3jiqHkB5GkKJ2jawamd6S5Y2XhCrONl3AP8NeJi9Gexp3Fz5YV7uj3/mRNlybAfuraxuKYJ/6HAKrCeuCnf5Mnm5kNPsM5sCNyFe0Sl7gGYlaCic9n2FWxPjiXFWASYv9LsRlPpH+Hziz9TUeAwvjEQrCZhShAn892rur7CNhALEMxCN5s3KsLvspxtWZ7nPvOG7z+yGxsG5dfJ7HbDGsN8s7VMY1WsPb11GvvuDSMGdfmTKlZcQ mo1R79I5 ngBFjG3EN9Fqx7FN3DK+1WxhA5pIcdOSi/2x16L83G2oXH3hSK7cYw9t0rBiz2qdWJhTfpYWXG1lEXACqVExt2YYqcx2CN6DJLI4oi2X14+ajMaPByZcYSNNSOP7m2dcEvazsFbC43jHJAkMfDjbSGYhCy4Y/XX9qjvsyEfpZChAIURHb/mwfReWNTBoNCAV2McIWOpNvD183s8nbESDUlUycgjfBeBTGjGuSAI3y76OCHHuVNGYb5ebi214O2QHv3ZHTE02nVNaZjw1lOPHzIuFTfD5gPXaB2rV1hgHxtKpJtoieG0+RgFK6NOpR4c5e6WrmxUi4A8XRLSnjhB91q1qpxnTMv4twlPX3N5HF5n48yPqeYtmH2UglvC7LV5aC1yzQ/mEUMB2xillqywVFCS+y43/T7mfQ537M9ldY6JgfbQWAFVTdjYXxxiqNXiR7SoyFOtAX8CjlKsI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidation. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 4 ++++ tools/arch/x86/include/asm/msr-index.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9a71880eec07..a7ea9720ba3c 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 3e8180354303..38f454671c88 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1075,6 +1075,10 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); + + /* Enable Translation Cache Extension */ + if (cpu_feature_enabled(X86_FEATURE_TCE)) + msr_set_bit(MSR_EFER, _EFER_TCE); } #ifdef CONFIG_X86_32 diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..dc1c1057f26e 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /*