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b=VewRmgT4Dw/0QZrGgJKtARJfUDtEP/d4/Pfbimo7tIuAjacS8gLiz5/CNGZ6FQx874byrW /dcsBVwzDcTO30wbMuHWGFgI1IB22EkFiT8Vy5EvvVNpCbbCX8qE4u7jiPpStLHTJCXnww IrDSxLq3PLuunuAM3A3tX3RqWKdF8/E= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740340274; a=rsa-sha256; cv=none; b=A0IblRKILXyqiyopjKxxidDkngh7UaWFcDXJNkGaa9o5hMTML0l24PxTGb46oH5swe8O9R /aOdEcTDAS/QDjssSXueQ/ogMAriFbjiCymnCmEUAqyHMw6zReMf8Niz2TJJxiQPhQ7CE+ 99udDsGT4gRKR/RxJAlcNLBA9hA525Y= ARC-Authentication-Results: i=1; imf04.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf04.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tmHyy-000000001hX-3i4A; Sun, 23 Feb 2025 14:49:44 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org, Rik van Riel , Dave Hansen Subject: [PATCH v13 03/14] x86/mm: add INVLPGB support code Date: Sun, 23 Feb 2025 14:48:53 -0500 Message-ID: <20250223194943.3518952-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250223194943.3518952-1-riel@surriel.com> References: <20250223194943.3518952-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 4DAD140002 X-Rspamd-Server: rspam07 X-Stat-Signature: 9x6eg3rpdyriksmfp3s5wrz5fjxbfxw7 X-HE-Tag: 1740340274-151047 X-HE-Meta: U2FsdGVkX19/JX4z1aptF0LSN3B5aQmaDmHmGYNL1CK1LvSqc4mg9dY1nquuCh7wO5HMiSdL9jY2yW1qf2TNdDjsllADoeefHmM7Y+4BcOF1cNkBRZwANp8BjgoEr/vALkm74yjjxEq4GpOjg2D/EcGxx5qpENmLl6OVR+g7Cwe5l1zU4u6uxO2ZhRgxJsCr120SHqSQ+CRjlnTwb5tR2eMttSxUNZUh/grRRWlLVIzwJNKJN/RaQNwj2TZTEt8uZDfOnfmbbi1sv+k77OcujVMCt78sZNwA0ZHzf8HPN/lXhtJUTuR8v89asyF09NcpAOiTSYekc88FnEUUMXY/Eb8oQT3t6UztA7iaefXyBoTGxQJLBXEUL2Dg08kqPlgw2iU0pUtVcMFpWMhj+wzD5RIcfXJlnJfoi0aEh/na7XUW6T82sBy5KxIXtimSXqSmGI+DF8Wu++QnjIGJMfdJ0b9DsiqsOwmAgQ24zSt0A7+jbKNKRRNQUDYkRv2kJWAmz0dVKrUo34qm9Z68Thrhk/WIiSjt2VSU4t1r88u6nDAr7HDz0SOzV+vikWgQz0whNQ+We87ZUekGJRrRKQp3UBZGaQP2rpAq4zMPp0Jkw00MrVtEASF5QAD0tUV845c84iLJOXF2X/mkOiv3P2FGU4TiwcaSSufJYXxFW6J31AzqCX6GJ18RSMLQAFUP88dhJYZUrvKuoPSpPwQsswMCuj0t9It1Y3Ihm9cigv/ar7RZlmrQr/RYNHSHlIfTCzY7VPLB14cTDV9vE5oa8hWQPmiQJoh5ivh9FfgWTocBeZQWucKZN4FFvz1jZZDWQomiiQTsvwDZsSK9ei6PDOuUWx3NtjLOwd62biRT3AygJAXKfYkF4MJ0/6iuzGXOnYJ0irItxH/tABgbKUNoFobFPgiPsAXxmE7N3yIchCn0uDJHqK0qJP58iIsyRs4AxYX9SVcHlsDFVc2haXizoNK h5kFbaIN MsjFIl22YPEI6aFYwddDjJWK1dVWjU7GBwGbnTxt7xNFovwVCRBPQTul/6VpvqBMHCVTpg2J3c9k2D0wq4ksDn6NWXIiP9NpNPrgInirbPAATBkvMJzOeM0w2+D2bz7CRmN0uYqKHMwMDl8zidukIY3/KU1J6C/TesYzg2oiiKyaMJyBe9XrE7R3baxdak+uaa3z3nJv0Y4qzi8uPgQmRcYcD/86qIljb/of2SpegilgI1nVcKu2Vpf8iDaGWNazcepPwG9YDrQAb0V4USWFq/xqFr/+X3vGHu2GX/aax4pHVOnxnydHrTS685EC1U5TftGPPPf8fvHRx815F9vBF4W4JlwPyl1md0F2i11nD+EXLtbSDMo+tlZWLRibw+LPz88JqLJLvoqJpDk6tfB0pYxoeWr3Q1lO80NFSEpj+Ghv+emra4/EH2FZeF/PtPI70a+PbHN4TxCBVbpseMyoByJY6nV7wAi/E2cdj X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. All the functions defined in invlpgb.h are used later in the series. Compile time disabling X86_FEATURE_INVLPGB when the config option is not set allows the compiler to omit unnecessary code. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley Acked-by: Dave Hansen --- arch/x86/include/asm/disabled-features.h | 9 ++- arch/x86/include/asm/tlb.h | 92 ++++++++++++++++++++++++ 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c492bdc97b05..95997caf0935 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -129,6 +129,13 @@ #define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) #endif +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +#define DISABLE_INVLPGB 0 +#else +/* Keep 32 bit kernels smaller by compiling out the INVLPGB code. */ +#define DISABLE_INVLPGB (1 << (X86_FEATURE_INVLPGB & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -146,7 +153,7 @@ #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK) #define DISABLED_MASK12 (DISABLE_FRED|DISABLE_LAM) -#define DISABLED_MASK13 0 +#define DISABLED_MASK13 (DISABLE_INVLPGB) #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h index 77f52bc1578a..b3cd521e5e2f 100644 --- a/arch/x86/include/asm/tlb.h +++ b/arch/x86/include/asm/tlb.h @@ -6,6 +6,9 @@ static inline void tlb_flush(struct mmu_gather *tlb); #include +#include +#include +#include static inline void tlb_flush(struct mmu_gather *tlb) { @@ -25,4 +28,93 @@ static inline void invlpg(unsigned long addr) asm volatile("invlpg (%0)" ::"r" (addr) : "memory"); } + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * The instruction takes the number of extra pages to invalidate, beyond + * the first page, while __invlpgb gets the more human readable number of + * pages to invalidate. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, + unsigned long addr, u16 nr_pages, + bool pmd_stride, u8 flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31) | (nr_pages - 1); + u64 rax = addr | flags; + + /* The low bits in rax are for flags. Verify addr is clean. */ + VM_WARN_ON_ONCE(addr & ~PAGE_MASK); + + /* INVLPGB; supported in binutils >= 2.36. */ + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void __tlbsync(void) +{ + cant_migrate(); + /* TLBSYNC: supported in binutils >= 0.36. */ + asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 1, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 1, 0, INVLPGB_INCLUDE_GLOBAL); + __tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb(0, 0, addr, nr, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 1, 0, 0); + __tlbsync(); +} + #endif /* _ASM_X86_TLB_H */