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b=A+66bsBrI6LnD4/ghSO9Q26I2AWTlEkHiLAFu58B/J+msjrG5Q/Yn2hy177AbFbExfkDa0 rVOlTkY+h0qefZ9xx207PB9JEqc8NLIDlc2MZD6sfOBUrh7hrM0ieZBlMYlPclghcdKFau D5EJQZCUF7D9LkKoWXWskeZiTg/hRKE= ARC-Authentication-Results: i=1; imf01.hostedemail.com; dkim=none; spf=pass (imf01.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740538948; a=rsa-sha256; cv=none; b=SHWf+THIu6TFxjBZBS5dU+W3WnI53k6EbBPDsJMrt4+d94wM0FMQUd86KjnMDIQPnZyZPj buEPr4lvs39lHuy5rk+pvD7VK6Oobu7QubE2kES5LIkrpbFcPHMiyBW3U0XAFNnrDktZqF a5Zg+tSR+NAr20jEkct55HjmRSPmIFE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tn7fw-000000001Y5-0aUg; Tue, 25 Feb 2025 22:01:32 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org, Rik van Riel , Dave Hansen Subject: [PATCH v14 03/13] x86/mm: add INVLPGB support code Date: Tue, 25 Feb 2025 22:00:38 -0500 Message-ID: <20250226030129.530345-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250226030129.530345-1-riel@surriel.com> References: <20250226030129.530345-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 5B89140007 X-Stat-Signature: xq6mdwwkqkrkdzzydfa5ja7ebbraouhc X-Rspamd-Server: rspam03 X-HE-Tag: 1740538948-604677 X-HE-Meta: U2FsdGVkX1/yg3SWCc7vkXFjOXbRrSpYV96EgffMgLv20/c1c1DJDdpmCUw8s4qC7TYonuT395EgfTFclnE5wD5JNs8LnbvatkFqwzbnv3Epmkinans2KoBTuI2ABsLvve8CfJ6bQbBs/f+v0wvZl5Kgg6rgzvQtCHHWSZQsKjZCF3ZNfG0D+YN9ra5tCVZVKLm40ZJgpsKCDL8nfcAqz4JSgDZRwhKjvdRElUpeYoVdhYO04vh4OAhsnA/Tt9/Sr3KE9m+QcSCuH9tMFimp1Jy+6YR73vF1xhMey1tZ4icYC2PME2YGXWsB/QfJuDBJDTawhufab4rbuDAu/tE85q3O6R+p9s9KAWfFnHUCJYdCRsHaF4XI2nDJ2hezZRcFujo6uZM4d/MUqFX9jKQTGdn9qkdkWWEFgxslpf1AsY8/87agdfWx4jOwDOu0r55D/OWrG62opWf0XcaWZm4Ir74JFXMjgIlt+dYOj3YFLvTKeBmpW+im1I7FVngqFODZSGab3l6NsFPiumoPZGa6xl6kqcRktHuPJ8nZ0OX79NDOYb/iHn4KcThJrKfciD/jML0sN49B3g798dPoPipNl6Uu4twgh2KT97nG7gy+Nf+nZhTKbkVgq3NC8YDXguCaX86BqULq4Q/QSbKLjzJt4V65dRBHhShZ6KYWVP94lQNjqdbDbCxZMJY+wLmFZrnx4MwE5eIcAq6ekK5vOuvVEiL0AJocFkKVZVS9mpizQHAzml3hPybbkTbr8YCJranIiBr8mnkW6+p4L9fFKe+6XvTbP9BFXg8jLoszD3Cq+ORM7XlcAjAY2ZLgdXx4EDQ7ZZZfHJqcaFge618GlW6ggFmpMpQhE2SbELycuWme+aRQfGjPunV6wzmasTRUcyVf8WfJQua0811L0Of9L3rFGv5e0RGx/Nq9SvZ/EzFukXe3Qq5+gX5TpZSLWXkFnxHh0iGLRmVWRPd/z+TNVIi e9GCYnex gokdhLeHq65AuoFw7n6GZ47JuTNgjzbqj7mxPvV1ZSEJI3CH835szr5Mr9KLsCXQo/6kctF81Ajt0sBipmPiJTJwurAgBaghs7V9p5GzGjUNYfGsF3j5CypeWlEmVDI1oEk8bnBJ4LdIzYMRjuQdsffTyGXpoW132i+iSD8JC8NydYz6f+/LwARGrPRFTfeEE1ckVec8mH+1Js+UMCPW18j1nsNqu5eivqHadWAT/2gfag0J3mzSh0JVto1wSh7t0c/8GrtdvhQJ6OiFjB2yhoXjd+nIsSz7MAmZyUPNo9BmVl7KZSu2nRTT9vrYVjDORiBp/MHk8XTgYjFYjjsYugHXkhRhGg0SYintDKkgU/xhbDhbvDTv25FC8i4etPdImb6Bbh0AXxy89OjYtvRlbpZnP2NC1We5RmqNNCg4AnZ8tWUevV8IrpsCjRZqv5sppIpqv90eW97YHnuGhRrR+Zd1G5SIWhYMChggg X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. All the functions defined in invlpgb.h are used later in the series. Compile time disabling X86_FEATURE_INVLPGB when the config option is not set allows the compiler to omit unnecessary code. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley Acked-by: Dave Hansen --- arch/x86/include/asm/disabled-features.h | 8 +- arch/x86/include/asm/tlb.h | 98 ++++++++++++++++++++++++ 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c492bdc97b05..625a89259968 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -129,6 +129,12 @@ #define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) #endif +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +#define DISABLE_INVLPGB 0 +#else +#define DISABLE_INVLPGB (1 << (X86_FEATURE_INVLPGB & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -146,7 +152,7 @@ #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK) #define DISABLED_MASK12 (DISABLE_FRED|DISABLE_LAM) -#define DISABLED_MASK13 0 +#define DISABLED_MASK13 (DISABLE_INVLPGB) #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h index 77f52bc1578a..91c9a4da3ace 100644 --- a/arch/x86/include/asm/tlb.h +++ b/arch/x86/include/asm/tlb.h @@ -6,6 +6,9 @@ static inline void tlb_flush(struct mmu_gather *tlb); #include +#include +#include +#include static inline void tlb_flush(struct mmu_gather *tlb) { @@ -25,4 +28,99 @@ static inline void invlpg(unsigned long addr) asm volatile("invlpg (%0)" ::"r" (addr) : "memory"); } + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * The instruction takes the number of extra pages to invalidate, beyond + * the first page, while __invlpgb gets the more human readable number of + * pages to invalidate. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, + unsigned long addr, u16 nr_pages, + bool pmd_stride, u8 flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31) | (nr_pages - 1); + u64 rax = addr | flags; + + /* The low bits in rax are for flags. Verify addr is clean. */ + VM_WARN_ON_ONCE(addr & ~PAGE_MASK); + + /* INVLPGB; supported in binutils >= 2.36. */ + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +static inline void __tlbsync(void) +{ + /* + * tlbsync waits for invlpgb instructions originating on the + * same CPU to have completed. Print a warning if we could have + * migrated, and might not be waiting on all the invlpgbs issued + * during this TLB invalidation sequence. + */ + cant_migrate(); + + /* TLBSYNC: supported in binutils >= 0.36. */ + asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 1, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 1, 0, INVLPGB_INCLUDE_GLOBAL); + __tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb(0, 0, addr, nr, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 1, 0, 0); + __tlbsync(); +} + #endif /* _ASM_X86_TLB_H */