From patchwork Fri Mar 21 13:06:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 14025409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AE92C36000 for ; Fri, 21 Mar 2025 13:10:49 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 644E6280005; Fri, 21 Mar 2025 09:10:47 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 5F29C280001; Fri, 21 Mar 2025 09:10:47 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 495AA280005; Fri, 21 Mar 2025 09:10:47 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 2CCC6280001 for ; Fri, 21 Mar 2025 09:10:47 -0400 (EDT) Received: from smtpin06.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id 72A76C1DFF for ; Fri, 21 Mar 2025 13:10:48 +0000 (UTC) X-FDA: 83245592976.06.AD6E3FD Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by imf03.hostedemail.com (Postfix) with ESMTP id 607AF20022 for ; Fri, 21 Mar 2025 13:10:46 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=bgndQfWj; dmarc=none; spf=pass (imf03.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1742562646; a=rsa-sha256; cv=none; b=enkfWSFh4Mwzbteo/6tKzzbAkZNU6tOLNEk6wIgAqB8MrDIeqeWgAq19R7uOjr/QQY8vSz lJ63Hq06kySoTnjrs/Y6fizqQi6hgsZMK9F8yj/S4nseUgI2k14hObZPtxs4m4H2nSBJGM FszZPfQO1AGThvtl6Ih5d0n8jbhd6Qk= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=bgndQfWj; dmarc=none; spf=pass (imf03.hostedemail.com: domain of alexghiti@rivosinc.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=alexghiti@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1742562646; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=eAv+4atVMvRknGVbTPj58gq6ySa46Mekau0XoGNQASg=; b=x1gjs3xnvoutlM9uRS9pqEhzZQ9mI8NI2kc1rBASetfBcRrywLVghDPKbZYlcOsXLiwi0O XmFhrgQTJtzmAJ5z9WPYSUJuPKPWOVDzs/egZfAuCzGNrRSVJxgG47vRDjzO6QG3x6u4Pi oE5jHGEAIt+3ShfLhE54tKF4bZWYC+k= Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-43690d4605dso13286525e9.0 for ; Fri, 21 Mar 2025 06:10:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742562645; x=1743167445; darn=kvack.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eAv+4atVMvRknGVbTPj58gq6ySa46Mekau0XoGNQASg=; b=bgndQfWjcuLVd9r1P3Q+PVQlUTvZLkbIvECHYknmztWNDtWAi472Ke9OfvmjiYO/vw cC4OTxG0/tqlrgsZDh8jTFppSN4b0fA2VspZRdJnATg7zcR48v6Vfz41K7G26HW8lGZL oa6svHOOFHekc6Seyf8yiwhqOqoJS1sw9FqpZe9KBeyn5P/qZaWqGGitLs12qXuAP+VM jyzHqSqXLxGurg/nB+/sFxTANH0pLh5+zKhAqjkVIXg+bJFKXkQo5zpFNCIXdrYBlTfs iZ7fZjMc1mCQL/qfQIoJsMAld8J09XQanBieHP2hqyFro3Gw4MlrD5JiRUxxFbDarKmp NkAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742562645; x=1743167445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eAv+4atVMvRknGVbTPj58gq6ySa46Mekau0XoGNQASg=; b=E5tcN/j8YSUJ1oA+2jGLOAIpo3D77qLfaWR6MH8jnhxyovlMhTvUR/87nx0b6Ybbdt xlqDsmWCR217l5edOL5a9j0qDkNqXUzYK6Q/Tgwr2nZp8ZBnyZ8nzT9Cpias2KhKRkL9 djhlAlNPzdtDJ9Eh//3eEYJK8M2Y5pCaumACoTNDExlhtBzWN7rpKAq78rWuEqkAA8sB dhO4BJcH7lz+B8YL4sLKu02djbv1I59s6RczQNd24HFAeg2Xzuou3U8ekhAfKk7EZ2xx kdbmgJEorI0JIFLqph1ihIamTE3uCHDgPmrrX5O+cG/d1uQLTwMT9DxEzxcQHNh8gfYL rNgw== X-Forwarded-Encrypted: i=1; AJvYcCUHPwCFSGStvehePTZvf7VaJHDWOoec9VLVgfwy989Ub+kGzlce1/Z0UjzMACqGBXjV+qPezy49Ew==@kvack.org X-Gm-Message-State: AOJu0YzwvhWiz2dFbMw5dG7J2TUBTOLDPcDLOeHl70mRsSmrev85/3DZ QL0RDbam3SC1Ju4MMmK17tWT9i+dMqzhgnKKZ0ifzNV+rjCmk4fagpRTNcFkLwM= X-Gm-Gg: ASbGnctwFP9ZoaQAHifN8ObATsVi8rCU6a+CqZ0hFNE1fQbhjog93dtIqhOlPUI0YIW EIrE1GT2yV+vWo4KyCfdrnHuk98Ym6kUnKFBTcMyQhmndgBhOJX5aidr3dUwynAUTGmPO1d3VR5 3OErj19SDeWnHq/G1AVxu77TiPXCr3d7SPkltzBno3lrsKjGvWriB9kIghB5ugnX5VE3/cgrVTs GQcunsIF4JTRz4xlg+98TBmjMQrUn/koKnyc+HbzY+ygxwSSWiOwnubpIMc74HebP3OI104ISTH cYLpDAn41Y2+PXYfQyAKVIlQeqUJZiQEl44JQHVyus1NJ/1fSE4v6D4TVyUFj7c9mptoLg== X-Google-Smtp-Source: AGHT+IFFzxLTl7dkoWPQa6CIZER6lpnHzrVNqhIgyBgY3Y3nEtgERu0W1NS2+ffacirYXfcMWjF6NQ== X-Received: by 2002:a05:600c:83cf:b0:439:91dd:cf9c with SMTP id 5b1f17b1804b1-43d509ec70cmr37202275e9.10.1742562644586; Fri, 21 Mar 2025 06:10:44 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com ([2001:861:3382:ef90:3d12:52fe:c1cc:c94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d42b8fcd4sm47982695e9.1.2025.03.21.06.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 06:10:44 -0700 (PDT) From: Alexandre Ghiti To: Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Matthew Wilcox , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH v5 4/9] mm: Use common set_huge_pte_at() function for riscv/arm64 Date: Fri, 21 Mar 2025 14:06:30 +0100 Message-Id: <20250321130635.227011-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250321130635.227011-1-alexghiti@rivosinc.com> References: <20250321130635.227011-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 607AF20022 X-Stat-Signature: t7q1dyp4jrinmpnsk3rqi1i5cxxc9ynw X-HE-Tag: 1742562646-355016 X-HE-Meta: U2FsdGVkX18dFX4SnjWjKjUB+bqNga2e2sSEAEalttju/gQ2KCUiBPMhecbdADWyzee8zcOuTeGUdU/bfwXOC19Pw8L85fSuUj2sKpF/eZNZ7jf7eaE+afCDeXCbeVPTBCMAL6LNIPVd9AoeqyZWecQ2Hc0HKQZ5om8uKvh3MqtbFpqPdOxeEBCZh+eaPxVlCDvYJ3++TF2EOifvDk3TZ5N7e9OgD9ZRChweY31w2lX9X8yQCgMNK0WV6zmG4GL7LODMqQ1of2IlLbkiwNNKv/xCeg4g8J/VMBgEBFJDrc9nivy/+FFbQS6ZcvzP4OnlqLfCvVX8ibGC5vhSoBZ3L9Uyf/p1KcrM9d1CRUXB3eq7z9q6sSxXXW1KbhB3mSH2XbP5vdKak0EipTxVipGEIFfK2hGnEV0VLskbrCCreW3+OY+8oNmRWRTKgF9rwX+EGczlrdfixMfwD8iL5OAtQs3/ryXBuSeAPsWelbg7Ee0s8kq+uHNarsGtbWJQ/aYxm/0EC/mzdKMXh2cRt/haE6ytonV55B57U7bLE8twPiskxZs95HNrKmCRwMBL54Ugb0TUmA75WwIdycWZDghB4wA1klhMiDG9+VY+yMstF8SEutoICaIoZ2B92d3FJENxnZDXqK+DmZIi2bqly0B9A29jGa2+zcqG1Vezn4Bk6p+htcmCyDuIShvQpIWFLbBD9vEPTUetUgjSB7pG/3Fmb2MqFhQJyPGv128fK213iiunkIV9nYmseR5eaM/agMFuRMWsrBbxfVpuHnNcY9gptrzy6DxQ4WGlk0H7SICNap9nWVSgKlQMANfs3kCeOzCWW4crE4Sqzxaz8E5SL4e/+ZgYC4/VPbbsRm1r+3Sah813ZxrNPzYGVtNf8JyD35nzwAByJZBlaGf0ss9lXUTOHE7sVbnRdGyOWb/WgzrQUavStUYyRaE/QX3CtyMyrvmGNglKRfffP+X9i6hN3jA QLhIf5gR tWWYJPCuGaC2ROj0HJam/af5ag2r7n8RmdReOo4u2VQ9na2tiB2mq6fsH9cq6uNsslBnbkwKvI5PpGrTEcTby1IqJKW0mYH1QV+Ej14Q3W6nzFlu6KPbL14Gj6QagNzO28/GNKXSX8Dgen1BVKgtDkesFCzyYr7HmKOdJLMqkh5JhEJSo4XExZ5mgzoo8I+ZtSvdFwB0zny6WFCMwxugTwCYSuKMFuqSIAz6Ck8TOSHPRyOi6IFdF84QFbfSRJtcG0u6xVRA213yhyjfPlI73r3ugcLIuPguZChxMsgBIiWyC1kYQHaG7xcpTIrYUzxwa5sZqfVnex26un+Gp2rBmMzGPK6TGbnILRk2owCMD7gYaJyK8EAtgR5bIyB96X8Y6pTWn9qQWt0oSiUk/ShLVnPLNv8UdVIq6PN7XkVVnTI4WS6UVG4DhpOUGO91tG0wiKCfKUiyhETWroO8YZyCdzWjL3g== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: After some adjustments, both architectures have the same implementation so move it to the generic code. Signed-off-by: Alexandre Ghiti --- arch/arm64/include/asm/hugetlb.h | 3 -- arch/arm64/mm/hugetlbpage.c | 56 -------------------------------- arch/riscv/include/asm/hugetlb.h | 5 --- arch/riscv/include/asm/pgtable.h | 13 ++++---- arch/riscv/mm/hugetlbpage.c | 50 ---------------------------- include/linux/hugetlb_contpte.h | 5 +++ mm/hugetlb_contpte.c | 56 ++++++++++++++++++++++++++++++++ 7 files changed, 68 insertions(+), 120 deletions(-) diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h index 0604e01dca97..cfdc04e11585 100644 --- a/arch/arm64/include/asm/hugetlb.h +++ b/arch/arm64/include/asm/hugetlb.h @@ -35,9 +35,6 @@ static inline void arch_clear_hugetlb_flags(struct folio *folio) pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags); #define arch_make_huge_pte arch_make_huge_pte -#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT -extern void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte, unsigned long sz); #define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS extern int huge_ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c index 60a2bb7575c1..6feb90ed2e7d 100644 --- a/arch/arm64/mm/hugetlbpage.c +++ b/arch/arm64/mm/hugetlbpage.c @@ -128,62 +128,6 @@ static pte_t get_clear_contig_flush(struct mm_struct *mm, return orig_pte; } -/* - * Changing some bits of contiguous entries requires us to follow a - * Break-Before-Make approach, breaking the whole contiguous set - * before we can change any entries. See ARM DDI 0487A.k_iss10775, - * "Misprogramming of the Contiguous bit", page D4-1762. - * - * This helper performs the break step for use cases where the - * original pte is not needed. - */ -static void clear_flush(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - unsigned long pgsize, - unsigned long ncontig) -{ - struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); - unsigned long i, saddr = addr; - - for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) - __ptep_get_and_clear(mm, addr, ptep); - - flush_tlb_range(&vma, saddr, addr); -} - -void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte, unsigned long sz) -{ - size_t pgsize; - int i; - int ncontig; - unsigned long pfn, dpfn; - pgprot_t hugeprot; - - ncontig = arch_contpte_get_num_contig(ptep, sz, &pgsize); - - if (!pte_present(pte)) { - for (i = 0; i < ncontig; i++, ptep++, addr += pgsize) - __set_ptes(mm, addr, ptep, pte, 1); - return; - } - - if (!pte_cont(pte)) { - __set_ptes(mm, addr, ptep, pte, 1); - return; - } - - pfn = pte_pfn(pte); - dpfn = pgsize >> PAGE_SHIFT; - hugeprot = pte_pgprot(pte); - - clear_flush(mm, addr, ptep, pgsize, ncontig); - - for (i = 0; i < ncontig; i++, ptep++, addr += pgsize, pfn += dpfn) - __set_ptes(mm, addr, ptep, pfn_pte(pfn, hugeprot), 1); -} - pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long sz) { diff --git a/arch/riscv/include/asm/hugetlb.h b/arch/riscv/include/asm/hugetlb.h index 69393346ade0..7049a17b819d 100644 --- a/arch/riscv/include/asm/hugetlb.h +++ b/arch/riscv/include/asm/hugetlb.h @@ -24,11 +24,6 @@ bool arch_hugetlb_migration_supported(struct hstate *h); void huge_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep, unsigned long sz); -#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT -void set_huge_pte_at(struct mm_struct *mm, - unsigned long addr, pte_t *ptep, pte_t pte, - unsigned long sz); - #define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep, diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 286fe1a32ded..5b34b3c9c0f9 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -715,9 +715,8 @@ static inline pte_t pte_napot_clear_pfn(pte_t *ptep, pte_t pte) return pte; } -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -static inline pte_t ptep_get_and_clear(struct mm_struct *mm, - unsigned long address, pte_t *ptep) +static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, + unsigned long address, pte_t *ptep) { pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); @@ -775,9 +774,8 @@ static inline void __set_ptes(struct mm_struct *mm, unsigned long addr, #define set_ptes ___set_ptes #define __set_ptes ___set_ptes -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -static inline pte_t ptep_get_and_clear(struct mm_struct *mm, - unsigned long address, pte_t *ptep) +static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, + unsigned long address, pte_t *ptep) { pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); @@ -787,6 +785,9 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm, } #endif /* CONFIG_RISCV_ISA_SVNAPOT */ +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR +#define ptep_get_and_clear __ptep_get_and_clear + #define pgprot_nx pgprot_nx static inline pgprot_t pgprot_nx(pgprot_t _prot) { diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c index b9eb6b7b214d..75faeacc8138 100644 --- a/arch/riscv/mm/hugetlbpage.c +++ b/arch/riscv/mm/hugetlbpage.c @@ -176,56 +176,6 @@ pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags) return entry; } -static void clear_flush(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - unsigned long pgsize, - unsigned long ncontig) -{ - struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); - unsigned long i, saddr = addr; - - for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) - ptep_get_and_clear(mm, addr, ptep); - - flush_tlb_range(&vma, saddr, addr); -} - -/* - * When dealing with NAPOT mappings, the privileged specification indicates that - * "if an update needs to be made, the OS generally should first mark all of the - * PTEs invalid, then issue SFENCE.VMA instruction(s) covering all 4 KiB regions - * within the range, [...] then update the PTE(s), as described in Section - * 4.2.1.". That's the equivalent of the Break-Before-Make approach used by - * arm64. - */ -void set_huge_pte_at(struct mm_struct *mm, - unsigned long addr, - pte_t *ptep, - pte_t pte, - unsigned long sz) -{ - size_t pgsize; - int i, pte_num; - - pte_num = arch_contpte_get_num_contig(ptep, sz, &pgsize); - - if (!pte_present(pte)) { - for (i = 0; i < pte_num; i++, ptep++, addr += pgsize) - set_ptes(mm, addr, ptep, pte, 1); - return; - } - - if (!pte_napot(pte)) { - set_ptes(mm, addr, ptep, pte, 1); - return; - } - - clear_flush(mm, addr, ptep, pgsize, pte_num); - - set_ptes(mm, addr, ptep, pte, pte_num); -} - int huge_ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, diff --git a/include/linux/hugetlb_contpte.h b/include/linux/hugetlb_contpte.h index 2ea17e4fe36b..135b68bd09ca 100644 --- a/include/linux/hugetlb_contpte.h +++ b/include/linux/hugetlb_contpte.h @@ -9,4 +9,9 @@ #define __HAVE_ARCH_HUGE_PTEP_GET extern pte_t huge_ptep_get(struct mm_struct *mm, unsigned long addr, pte_t *ptep); +#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT +extern void set_huge_pte_at(struct mm_struct *mm, + unsigned long addr, pte_t *ptep, pte_t pte, + unsigned long sz); + #endif /* _LINUX_HUGETLB_CONTPTE_H */ diff --git a/mm/hugetlb_contpte.c b/mm/hugetlb_contpte.c index 500d0b96a680..cbf93ffcd882 100644 --- a/mm/hugetlb_contpte.c +++ b/mm/hugetlb_contpte.c @@ -30,3 +30,59 @@ pte_t huge_ptep_get(struct mm_struct *mm, unsigned long addr, pte_t *ptep) } return orig_pte; } + +/* + * ARM64: Changing some bits of contiguous entries requires us to follow a + * Break-Before-Make approach, breaking the whole contiguous set + * before we can change any entries. See ARM DDI 0487A.k_iss10775, + * "Misprogramming of the Contiguous bit", page D4-1762. + * + * RISCV: When dealing with NAPOT mappings, the privileged specification + * indicates that "if an update needs to be made, the OS generally should first + * mark all of the PTEs invalid, then issue SFENCE.VMA instruction(s) covering + * all 4 KiB regions within the range, [...] then update the PTE(s), as + * described in Section 4.2.1.". That's the equivalent of the Break-Before-Make + * approach used by arm64. + * + * This helper performs the break step for use cases where the + * original pte is not needed. + */ +static void clear_flush(struct mm_struct *mm, + unsigned long addr, + pte_t *ptep, + unsigned long pgsize, + unsigned long ncontig) +{ + struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0); + unsigned long i, saddr = addr; + + for (i = 0; i < ncontig; i++, addr += pgsize, ptep++) + __ptep_get_and_clear(mm, addr, ptep); + + flush_tlb_range(&vma, saddr, addr); +} + +void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte, unsigned long sz) +{ + size_t pgsize; + int i; + int ncontig; + + ncontig = arch_contpte_get_num_contig(ptep, sz, &pgsize); + + if (!pte_present(pte)) { + for (i = 0; i < ncontig; i++, ptep++, addr += pgsize) + __set_ptes(mm, addr, ptep, pte, 1); + return; + } + + if (!pte_cont(pte)) { + __set_ptes(mm, addr, ptep, pte, 1); + return; + } + + clear_flush(mm, addr, ptep, pgsize, ncontig); + + set_contptes(mm, addr, ptep, pte, ncontig, pgsize); +}