From patchwork Mon Nov 2 16:03:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 11874265 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B3EC92A for ; Mon, 2 Nov 2020 16:04:46 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 245F922258 for ; Mon, 2 Nov 2020 16:04:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=google.com header.i=@google.com header.b="M1egA/6R" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 245F922258 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 7E1816B0083; Mon, 2 Nov 2020 11:04:43 -0500 (EST) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 7B7196B0085; Mon, 2 Nov 2020 11:04:43 -0500 (EST) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 6A5CA6B0087; Mon, 2 Nov 2020 11:04:43 -0500 (EST) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0222.hostedemail.com [216.40.44.222]) by kanga.kvack.org (Postfix) with ESMTP id 313B56B0083 for ; Mon, 2 Nov 2020 11:04:43 -0500 (EST) Received: from smtpin28.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id B09703632 for ; Mon, 2 Nov 2020 16:04:42 +0000 (UTC) X-FDA: 77439951204.28.park22_2a0fbc7272b1 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin28.hostedemail.com (Postfix) with ESMTP id 758E86C26 for ; Mon, 2 Nov 2020 16:04:42 +0000 (UTC) X-Spam-Summary: 1,0,0,996ef5b189634519,d41d8cd98f00b204,3gs6gxwokcpgfsiwj3ps0qlttlqj.htrqnsz2-rrp0fhp.twl@flex--andreyknvl.bounces.google.com,,RULES_HIT:41:152:355:379:541:800:960:973:988:989:1260:1277:1313:1314:1345:1359:1431:1437:1516:1518:1535:1543:1593:1594:1711:1730:1747:1777:1792:2393:2559:2562:2895:2899:2901:3138:3139:3140:3141:3142:3152:3355:3865:3866:3867:3868:3870:3871:3872:3874:4117:4250:4321:4605:5007:6117:6119:6261:6653:6742:7576:7903:9969:10004:10400:11026:11232:11473:11657:11658:11914:12043:12291:12296:12297:12438:12555:12679:12895:12986:13138:13141:13161:13180:13229:13230:13231:13868:14181:14394:14659:14721:21080:21365:21444:21451:21627:21795:30051:30054:30070,0,RBL:209.85.160.202:@flex--andreyknvl.bounces.google.com:.lbl8.mailshell.net-66.100.201.100 62.18.0.100;04y8ga33fpmu338nfaky11uanjckmock3n79ejjthyj3jrggozru9dy9umzirkb.4moduoupyd5ioqfw93janfza3jbbkkms4pg8n7ydezeee7hu4e31psadpwa4pjz.h-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5,0.5,N etcheck: X-HE-Tag: park22_2a0fbc7272b1 X-Filterd-Recvd-Size: 6827 Received: from mail-qt1-f202.google.com (mail-qt1-f202.google.com [209.85.160.202]) by imf50.hostedemail.com (Postfix) with ESMTP for ; Mon, 2 Nov 2020 16:04:41 +0000 (UTC) Received: by mail-qt1-f202.google.com with SMTP id h31so8312390qtd.14 for ; Mon, 02 Nov 2020 08:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=VsN8c2WI1TMox3v/PYtKI3bTw78pIVnf1hcHZhXvdoM=; b=M1egA/6RbV9qQ9SDV7wZ1UNoR8Pff1wFC083SCkcQKfnsgv5twQ9bSOeF6rIAyg+q2 yuRY0m5AolHyr8nnEh+8NBFAlt7ssj5pWCjb17HiDGHQxVxtN9OlrnZjUgDY53yVfPcw rskl85yGKC+v3r+N0dWw0FqRblNFA/7CsbHI237wQCKQVCdVZ8kLSDeqxxrZr1NdenZa Fk0bFuqEvsrq30pbklqr+tiub1M6DMTGkEqrRFYmTl0hsKMi7H3odK3d6/d+eVcOavSk hcSt21DIUaZFd4YwaEmnFxqFbh0YF6mVD/aWO9zkZ9j90K1Nns2c0YbHw+/32lkoDI5V UDhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=VsN8c2WI1TMox3v/PYtKI3bTw78pIVnf1hcHZhXvdoM=; b=tCPP8efw0ELZq3ZqiUUPA8c/aZ5iyivpBtbZrs3IMVr5cvFIhWO4fz3JRZlvofWHpr BUzMM5ypW039+jrkStvkkQpwsorM2JWNZ07cxRy8CR4NRBMQCTCbGtFSBHFotBK+al34 POBO0S2hntWqtQlg3kbSNbo+hUDOAjN9aCg3db1FW4LRl7N/geZKmDaEHUuUHSRQjfIT ykQGOAF5rIfZzqieDmQwZhjmqI3IdSUVAwhnTN5+8FkZEL1dN0+yx6o04wyZ/qcOHZJ+ RuAu60LJYmLJQ2REqdSH+yg8qLMMfyG6ifSvIHiU8wK0r55zWjx+kj5hRrOK/fXn3yS1 hYzQ== X-Gm-Message-State: AOAM530XDotMpZZAHbxS9gHVWqpfPs9QMkWRSglruv1mBOxOmpwC1n9s tnEMx0s6RD2qehE8oxmEJiLvyZycxdqBXf4S X-Google-Smtp-Source: ABdhPJwRjdkGZcpAEGzSh4QMc5CdQQ+dmOJxKegYoZaSvVJf05B349Ft5a4YLWBwLaS6ou5tXYI8GpFINX8AdZHL X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:a0c:baa2:: with SMTP id x34mr22633076qvf.23.1604333081018; Mon, 02 Nov 2020 08:04:41 -0800 (PST) Date: Mon, 2 Nov 2020 17:03:46 +0100 In-Reply-To: Message-Id: <29259e315987b3cff3c6bf2ebac9cc089b7413a0.1604333009.git.andreyknvl@google.com> Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v7 06/41] arm64: kasan: Enable in-kernel MTE From: Andrey Konovalov To: Catalin Marinas , Will Deacon Cc: Vincenzo Frascino , kasan-dev@googlegroups.com, Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrey Konovalov X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Vincenzo Frascino Hardware tag-based KASAN relies on Memory Tagging Extension (MTE) feature and requires it to be enabled. The Tag Checking operation causes a synchronous data abort as a consequence of a tag check fault when MTE is configured in synchronous mode. Enable MTE in Synchronous mode in EL1 to provide a more immediate way of tag check failure detection in the kernel. As part of this change enable match-all tag for EL1 to allow the kernel to access user pages without faulting. This is required because the kernel does not have knowledge of the tags set by the user in a page. Note: For MTE, the TCF bit field in SCTLR_EL1 affects only EL1 in a similar way as TCF0 affects EL0. MTE that is built on top of the Top Byte Ignore (TBI) feature hence we enable it as part of this patch as well. Signed-off-by: Vincenzo Frascino Signed-off-by: Andrey Konovalov Reviewed-by: Catalin Marinas --- Change-Id: I4d67497268bb7f0c2fc5dcacefa1e273df4af71d --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/mm/proc.S | 23 ++++++++++++++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index dcc165b3fc04..c61f201042b2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1704,6 +1704,13 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) cleared_zero_page = true; mte_clear_page_tags(lm_alias(empty_zero_page)); } + + /* Enable in-kernel MTE only if KASAN_HW_TAGS is enabled */ + if (IS_ENABLED(CONFIG_KASAN_HW_TAGS)) { + /* Enable MTE Sync Mode for EL1 */ + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); + isb(); + } } #endif /* CONFIG_ARM64_MTE */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 23c326a06b2d..7c3304fb15d9 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -40,9 +40,15 @@ #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA #ifdef CONFIG_KASAN_SW_TAGS -#define TCR_KASAN_FLAGS TCR_TBI1 +#define TCR_KASAN_SW_FLAGS TCR_TBI1 #else -#define TCR_KASAN_FLAGS 0 +#define TCR_KASAN_SW_FLAGS 0 +#endif + +#ifdef CONFIG_KASAN_HW_TAGS +#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 +#else +#define TCR_KASAN_HW_FLAGS 0 #endif /* @@ -427,6 +433,10 @@ SYM_FUNC_START(__cpu_setup) */ mov_q x5, MAIR_EL1_SET #ifdef CONFIG_ARM64_MTE + mte_tcr .req x20 + + mov mte_tcr, #0 + /* * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported * (ID_AA64PFR1_EL1[11:8] > 1). @@ -447,6 +457,9 @@ SYM_FUNC_START(__cpu_setup) /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr + + /* set the TCR_EL1 bits */ + mov_q mte_tcr, TCR_KASAN_HW_FLAGS 1: #endif msr mair_el1, x5 @@ -456,7 +469,11 @@ SYM_FUNC_START(__cpu_setup) */ mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ - TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS + TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS +#ifdef CONFIG_ARM64_MTE + orr x10, x10, mte_tcr + .unreq mte_tcr +#endif tcr_clear_errata_bits x10, x9, x5 #ifdef CONFIG_ARM64_VA_BITS_52