From patchwork Wed Mar 29 18:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: andrey.konovalov@linux.dev X-Patchwork-Id: 13193124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11D1AC6FD18 for ; Wed, 29 Mar 2023 18:38:04 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 8F2F46B0075; Wed, 29 Mar 2023 14:38:03 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 8259C900004; Wed, 29 Mar 2023 14:38:03 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 652CD900002; Wed, 29 Mar 2023 14:38:03 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 501FB6B0075 for ; Wed, 29 Mar 2023 14:38:03 -0400 (EDT) Received: from smtpin26.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay04.hostedemail.com (Postfix) with ESMTP id 0BA661A066B for ; Wed, 29 Mar 2023 18:38:03 +0000 (UTC) X-FDA: 80622795246.26.03D61C2 Received: from out-47.mta1.migadu.com (out-47.mta1.migadu.com [95.215.58.47]) by imf01.hostedemail.com (Postfix) with ESMTP id 5771140009 for ; Wed, 29 Mar 2023 18:38:00 +0000 (UTC) Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=linux.dev header.s=key1 header.b=oP2VA3+D; spf=pass (imf01.hostedemail.com: domain of andrey.konovalov@linux.dev designates 95.215.58.47 as permitted sender) smtp.mailfrom=andrey.konovalov@linux.dev; dmarc=pass (policy=none) header.from=linux.dev ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1680115080; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=R0ZTLDK0+ErC3gsprSGJ+tiVFRHa88yHqEYRk0ERiZ0=; b=FOPBTfoWf3QuRqY2IW89ACTCisxi4KgCJ0fMy3wGPbjBy/T7SKco+YapcCQn1FTUcQTRfO tK63VMi9ysnsDjORLSBRXsurN6yRChoMRb0MzCT6sLP4kKs/7S7ktW9Hbn+YSUvVXm3lEA s85rJAQ4B+Pd5jnq9YNICKL7lyKNgg4= ARC-Authentication-Results: i=1; imf01.hostedemail.com; dkim=pass header.d=linux.dev header.s=key1 header.b=oP2VA3+D; spf=pass (imf01.hostedemail.com: domain of andrey.konovalov@linux.dev designates 95.215.58.47 as permitted sender) smtp.mailfrom=andrey.konovalov@linux.dev; dmarc=pass (policy=none) header.from=linux.dev ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1680115080; a=rsa-sha256; cv=none; b=6RFyCU9HL0JtiwjH8a+j47VqVQhhgV37lqcdkAmc9ydfAnouzpN1ByzOMiyUhltxvkNCn6 /bGHe+q7A8nmeWoYo68TfU7ncwrq6EWRTpPrLFDkisEUe3Xs3piY8VjmfEtypk4UrwROhO EMn5RT93fNYlPeGs/NuMTe6y1lYEIAY= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1680115078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R0ZTLDK0+ErC3gsprSGJ+tiVFRHa88yHqEYRk0ERiZ0=; b=oP2VA3+D9Qr8dKR4UOrrmrc1+nxlHZsTDv96qHpFlLIIE0qAxFcHxNtGpjSuXYDtYGe7g0 R9YJpt11ce2lsJJGHndi0vAWGx+Lrt1/J0xo2kovQdSX5r6myxaV5UGnajysVl3a/fkg9M 5PYt++7HFPVvKJdr1l9qX0EEByPuMKk= From: andrey.konovalov@linux.dev To: Marco Elver , Catalin Marinas Cc: Andrey Konovalov , Alexander Potapenko , Dmitry Vyukov , Andrey Ryabinin , kasan-dev@googlegroups.com, Vincenzo Frascino , Will Deacon , linux-arm-kernel@lists.infradead.org, Peter Collingbourne , Evgenii Stepanov , Andrew Morton , linux-mm@kvack.org, Weizhao Ouyang , linux-kernel@vger.kernel.org, Andrey Konovalov Subject: [PATCH v2 3/5] arm64: mte: Rename TCO routines Date: Wed, 29 Mar 2023 20:37:46 +0200 Message-Id: <74d26337b2360733956114069e96ff11c296a944.1680114854.git.andreyknvl@google.com> In-Reply-To: References: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Stat-Signature: 5x5fo37obxhdbdyz5fknmxzz35mqjem5 X-Rspam-User: X-Rspamd-Queue-Id: 5771140009 X-Rspamd-Server: rspam06 X-HE-Tag: 1680115080-284705 X-HE-Meta: U2FsdGVkX18eGlJs9J/nw1ER5qb9JQPEpIxrZxVRGruYJuJOAkuz4Fp8Q3mkKZGQhvYOhBwceSLL9yEVpgp1YxHpFWhlkPZ2bLB/MPfJl5fGdU1NPF96dADaqR5ZLQgou5J0oFyUj2H30JAjHpUnkUHx9mrEraeR+FLIFqxq0LIYfGpEZN9Qcv+3vs90wHwMl4H8zz/i0sr/MZq+uDVBSjbNvPWAumN9+cSQBfO62OYLxnzUjLkHcR5EJnIzFr0MggktHx1On4GfKOymgq35/fMMizCf++LzLNwHi1zAmubiGCusWgym3MP1a0gOrfLvmEe1jbcLhI995jIZeD7I61QRC0UlaBpj1ITpZEgyfHdOYoX0Zp02Q1bRsXiLJDS3zBUqqWjFQHhG8R27ecGfhxuXOwGgwJjPr2knv/V36S5HcuFPnVLzsWCruxCTG/vA4/R3MwA0tj7zXnCY6RSorM9s/rT8fbfD+c4Y6JoWCzZgRUhNNbPQkKZoBUSgI6EjFYKpl357KXnTsW5/OEmO4tTs0Bhecg8pn9jX5tGN3kaf0rPp8MYx6qVORCzh7Mhth1be/bGFvTh+5Wh2xvFsHLPqV5K/uRdJ3EyOv9Phpmi8rpOESmo7LtorPULXKEfp6pdWihX3hW+gbxsEoGdztkmX0+HDMCrRNImjntWliLpd544KZd49aK8VgGED9GLGO4V+nXyKSIQyL9ciSUhbtCoh8oV37JaBqruWJV4mIkXE9XXSBrtAZFWQgRWqXVWlNMktlLBZgA7l7RnQPyjMGBLkHDt1hINk/SLzz+2PqfLoo26Tk2zTUAU40wwKHbBjwdAZR7fNMGZyLtdu5MXR5izJOgGJkAZ2T9R+NOqDlybRk1+O1eeieGfM+PaQXgddE5hqZ+QsKoF6JVjC99nVJRfRcEME3lPeAjr4vFtA8rI327G0hbiwpfv05FAX/zYOGjJWx/gEViPi3GhsiNK WEpUapBW Yue2vKWMRM1pm+387N3F6bI5aCoNEdLpJeMv+1PoOsGH+XQI29znutcwmS7hyKm2Y3WUaut+ZdEw5PkIqXXToIR95yhaqBZWC2/ixWLNscFk733OLyKbGsMaeZmsKjf9BL4cmsKORX23ZQFNKBzkefWURFjnQK/3CmU8EB8XF+634eTSnqc9UcBKyy3OeaLtsGKZkVxREJEopSKDtWQxao37+zu6XkgdBD452KKUA7grMVCbPfRNYM0+vJsPcpRS76zJkKfHuBfBft334U1Om6meHrPt+pHAHgMhl2oy+FIdEG4Bq/Uq6T+nYyw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Vincenzo Frascino The TCO related routines are used in uaccess methods and load_unaligned_zeropad() but are unrelated to both even if the naming suggest otherwise. Improve the readability of the code moving the away from uaccess.h and pre-pending them with "mte". Cc: Will Deacon Signed-off-by: Vincenzo Frascino Signed-off-by: Catalin Marinas Signed-off-by: Andrey Konovalov --- Chages v1->v2: - Drop __ from mte_disable/enable_tco names, as those functions are to be exported to KASAN code. --- arch/arm64/include/asm/mte-kasan.h | 81 +++++++++++++++++++++++++ arch/arm64/include/asm/mte.h | 12 ---- arch/arm64/include/asm/uaccess.h | 66 +++----------------- arch/arm64/include/asm/word-at-a-time.h | 4 +- 4 files changed, 93 insertions(+), 70 deletions(-) diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h index 9f79425fc65a..2e98028c1965 100644 --- a/arch/arm64/include/asm/mte-kasan.h +++ b/arch/arm64/include/asm/mte-kasan.h @@ -13,8 +13,73 @@ #include +#ifdef CONFIG_KASAN_HW_TAGS + +/* Whether the MTE asynchronous mode is enabled. */ +DECLARE_STATIC_KEY_FALSE(mte_async_or_asymm_mode); + +static inline bool system_uses_mte_async_or_asymm_mode(void) +{ + return static_branch_unlikely(&mte_async_or_asymm_mode); +} + +#else /* CONFIG_KASAN_HW_TAGS */ + +static inline bool system_uses_mte_async_or_asymm_mode(void) +{ + return false; +} + +#endif /* CONFIG_KASAN_HW_TAGS */ + #ifdef CONFIG_ARM64_MTE +/* + * The Tag Check Flag (TCF) mode for MTE is per EL, hence TCF0 + * affects EL0 and TCF affects EL1 irrespective of which TTBR is + * used. + * The kernel accesses TTBR0 usually with LDTR/STTR instructions + * when UAO is available, so these would act as EL0 accesses using + * TCF0. + * However futex.h code uses exclusives which would be executed as + * EL1, this can potentially cause a tag check fault even if the + * user disables TCF0. + * + * To address the problem we set the PSTATE.TCO bit in uaccess_enable() + * and reset it in uaccess_disable(). + * + * The Tag check override (TCO) bit disables temporarily the tag checking + * preventing the issue. + */ +static inline void mte_disable_tco(void) +{ + asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(0), + ARM64_MTE, CONFIG_KASAN_HW_TAGS)); +} + +static inline void mte_enable_tco(void) +{ + asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(1), + ARM64_MTE, CONFIG_KASAN_HW_TAGS)); +} + +/* + * These functions disable tag checking only if in MTE async mode + * since the sync mode generates exceptions synchronously and the + * nofault or load_unaligned_zeropad can handle them. + */ +static inline void __mte_disable_tco_async(void) +{ + if (system_uses_mte_async_or_asymm_mode()) + mte_disable_tco(); +} + +static inline void __mte_enable_tco_async(void) +{ + if (system_uses_mte_async_or_asymm_mode()) + mte_enable_tco(); +} + /* * These functions are meant to be only used from KASAN runtime through * the arch_*() interface defined in asm/memory.h. @@ -138,6 +203,22 @@ void mte_enable_kernel_asymm(void); #else /* CONFIG_ARM64_MTE */ +static inline void mte_disable_tco(void) +{ +} + +static inline void mte_enable_tco(void) +{ +} + +static inline void __mte_disable_tco_async(void) +{ +} + +static inline void __mte_enable_tco_async(void) +{ +} + static inline u8 mte_get_ptr_tag(void *ptr) { return 0xFF; diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h index 20dd06d70af5..c028afb1cd0b 100644 --- a/arch/arm64/include/asm/mte.h +++ b/arch/arm64/include/asm/mte.h @@ -178,14 +178,6 @@ static inline void mte_disable_tco_entry(struct task_struct *task) } #ifdef CONFIG_KASAN_HW_TAGS -/* Whether the MTE asynchronous mode is enabled. */ -DECLARE_STATIC_KEY_FALSE(mte_async_or_asymm_mode); - -static inline bool system_uses_mte_async_or_asymm_mode(void) -{ - return static_branch_unlikely(&mte_async_or_asymm_mode); -} - void mte_check_tfsr_el1(void); static inline void mte_check_tfsr_entry(void) @@ -212,10 +204,6 @@ static inline void mte_check_tfsr_exit(void) mte_check_tfsr_el1(); } #else -static inline bool system_uses_mte_async_or_asymm_mode(void) -{ - return false; -} static inline void mte_check_tfsr_el1(void) { } diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 5c7b2f9d5913..30ea7b5c3ccb 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -136,55 +136,9 @@ static inline void __uaccess_enable_hw_pan(void) CONFIG_ARM64_PAN)); } -/* - * The Tag Check Flag (TCF) mode for MTE is per EL, hence TCF0 - * affects EL0 and TCF affects EL1 irrespective of which TTBR is - * used. - * The kernel accesses TTBR0 usually with LDTR/STTR instructions - * when UAO is available, so these would act as EL0 accesses using - * TCF0. - * However futex.h code uses exclusives which would be executed as - * EL1, this can potentially cause a tag check fault even if the - * user disables TCF0. - * - * To address the problem we set the PSTATE.TCO bit in uaccess_enable() - * and reset it in uaccess_disable(). - * - * The Tag check override (TCO) bit disables temporarily the tag checking - * preventing the issue. - */ -static inline void __uaccess_disable_tco(void) -{ - asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(0), - ARM64_MTE, CONFIG_KASAN_HW_TAGS)); -} - -static inline void __uaccess_enable_tco(void) -{ - asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(1), - ARM64_MTE, CONFIG_KASAN_HW_TAGS)); -} - -/* - * These functions disable tag checking only if in MTE async mode - * since the sync mode generates exceptions synchronously and the - * nofault or load_unaligned_zeropad can handle them. - */ -static inline void __uaccess_disable_tco_async(void) -{ - if (system_uses_mte_async_or_asymm_mode()) - __uaccess_disable_tco(); -} - -static inline void __uaccess_enable_tco_async(void) -{ - if (system_uses_mte_async_or_asymm_mode()) - __uaccess_enable_tco(); -} - static inline void uaccess_disable_privileged(void) { - __uaccess_disable_tco(); + mte_disable_tco(); if (uaccess_ttbr0_disable()) return; @@ -194,7 +148,7 @@ static inline void uaccess_disable_privileged(void) static inline void uaccess_enable_privileged(void) { - __uaccess_enable_tco(); + mte_enable_tco(); if (uaccess_ttbr0_enable()) return; @@ -302,8 +256,8 @@ do { \ #define get_user __get_user /* - * We must not call into the scheduler between __uaccess_enable_tco_async() and - * __uaccess_disable_tco_async(). As `dst` and `src` may contain blocking + * We must not call into the scheduler between __mte_enable_tco_async() and + * __mte_disable_tco_async(). As `dst` and `src` may contain blocking * functions, we must evaluate these outside of the critical section. */ #define __get_kernel_nofault(dst, src, type, err_label) \ @@ -312,10 +266,10 @@ do { \ __typeof__(src) __gkn_src = (src); \ int __gkn_err = 0; \ \ - __uaccess_enable_tco_async(); \ + __mte_enable_tco_async(); \ __raw_get_mem("ldr", *((type *)(__gkn_dst)), \ (__force type *)(__gkn_src), __gkn_err, K); \ - __uaccess_disable_tco_async(); \ + __mte_disable_tco_async(); \ \ if (unlikely(__gkn_err)) \ goto err_label; \ @@ -388,8 +342,8 @@ do { \ #define put_user __put_user /* - * We must not call into the scheduler between __uaccess_enable_tco_async() and - * __uaccess_disable_tco_async(). As `dst` and `src` may contain blocking + * We must not call into the scheduler between __mte_enable_tco_async() and + * __mte_disable_tco_async(). As `dst` and `src` may contain blocking * functions, we must evaluate these outside of the critical section. */ #define __put_kernel_nofault(dst, src, type, err_label) \ @@ -398,10 +352,10 @@ do { \ __typeof__(src) __pkn_src = (src); \ int __pkn_err = 0; \ \ - __uaccess_enable_tco_async(); \ + __mte_enable_tco_async(); \ __raw_put_mem("str", *((type *)(__pkn_src)), \ (__force type *)(__pkn_dst), __pkn_err, K); \ - __uaccess_disable_tco_async(); \ + __mte_disable_tco_async(); \ \ if (unlikely(__pkn_err)) \ goto err_label; \ diff --git a/arch/arm64/include/asm/word-at-a-time.h b/arch/arm64/include/asm/word-at-a-time.h index 1c8e4f2490bf..f3b151ed0d7a 100644 --- a/arch/arm64/include/asm/word-at-a-time.h +++ b/arch/arm64/include/asm/word-at-a-time.h @@ -55,7 +55,7 @@ static inline unsigned long load_unaligned_zeropad(const void *addr) { unsigned long ret; - __uaccess_enable_tco_async(); + __mte_enable_tco_async(); /* Load word from unaligned pointer addr */ asm( @@ -65,7 +65,7 @@ static inline unsigned long load_unaligned_zeropad(const void *addr) : "=&r" (ret) : "r" (addr), "Q" (*(unsigned long *)addr)); - __uaccess_disable_tco_async(); + __mte_disable_tco_async(); return ret; }