From patchwork Mon Nov 2 16:03:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 11874267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89967697 for ; Mon, 2 Nov 2020 16:04:51 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 2646A22258 for ; Mon, 2 Nov 2020 16:04:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=google.com header.i=@google.com header.b="nzqwEq4v" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2646A22258 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 0DAA36B0087; Mon, 2 Nov 2020 11:04:50 -0500 (EST) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 08AB26B0088; Mon, 2 Nov 2020 11:04:50 -0500 (EST) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id EBB686B0089; Mon, 2 Nov 2020 11:04:49 -0500 (EST) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0162.hostedemail.com [216.40.44.162]) by kanga.kvack.org (Postfix) with ESMTP id BE86F6B0087 for ; Mon, 2 Nov 2020 11:04:49 -0500 (EST) Received: from smtpin01.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 47F96181AEF09 for ; Mon, 2 Nov 2020 16:04:49 +0000 (UTC) X-FDA: 77439951498.01.crush06_5408d3a272b1 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin01.hostedemail.com (Postfix) with ESMTP id 46F5810047E2E for ; Mon, 2 Nov 2020 16:04:45 +0000 (UTC) X-Spam-Summary: 1,0,0,9eacb5b71c2b9256,d41d8cd98f00b204,3gy6gxwokcpocpftg0mpxniqqing.eqonkpwz-oomxcem.qti@flex--andreyknvl.bounces.google.com,,RULES_HIT:41:69:152:355:379:541:800:960:973:988:989:1260:1277:1313:1314:1345:1359:1431:1437:1516:1518:1535:1544:1593:1594:1711:1730:1747:1777:1792:2393:2559:2562:2693:3138:3139:3140:3141:3142:3152:3355:3865:3867:3868:3871:3872:3874:4118:4250:4321:4605:5007:6261:6653:6742:7576:7903:9036:9969:10004:11026:11232:11473:11657:11658:11914:12043:12296:12297:12438:12555:12679:12895:13149:13161:13180:13229:13230:13972:14181:14394:14659:14721:21063:21080:21365:21433:21444:21451:21627:21795:21990:30051:30054:30070,0,RBL:209.85.221.73:@flex--andreyknvl.bounces.google.com:.lbl8.mailshell.net-66.100.201.100 62.18.0.100;04ygx87p194dtxugkshn3ttuzumxaocgprbxnrd48dq1wo6epqnn9xiqakbxpgq.xitp3yi4szohm6djsgkm3sjj6h94ug7mwznx8rguynqswbytftsjn6pnrw37mj7.n-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF X-HE-Tag: crush06_5408d3a272b1 X-Filterd-Recvd-Size: 7854 Received: from mail-wr1-f73.google.com (mail-wr1-f73.google.com [209.85.221.73]) by imf21.hostedemail.com (Postfix) with ESMTP for ; Mon, 2 Nov 2020 16:04:44 +0000 (UTC) Received: by mail-wr1-f73.google.com with SMTP id h8so6625039wrt.9 for ; Mon, 02 Nov 2020 08:04:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=LscJFjoJLVax370bbjjUkdBy9lfnLd5L4hR3aqcqMxs=; b=nzqwEq4vTT8NHX0FUtAmfwZIPpfNr+OUJMFzbti3OSrPs3NVjotzFBReNwTxYV6AMz HWgsOD2MpXBezJQXeaZw0TT7LWf3COshRTz2OUPwuDdwhfuUwnootXaOFUZ3C+GhC6cT J/q3KcCZWJahgOQAhs7OaEzaCrii4O+J1VWsZ2ZQD6JWbOc/QvwviNgeONWUVt2VFIz1 MTF7ac62CjoqIN8eI1hsQhKJkjS0B2HVumQOYzgTBMBHFgiOGUaaxD5MFX7KESHyZH3M fw3ivDHY2fFTfYVyqmOI/ypD3eT5UzJNjMO8K5qQJeL6EO0h2KSJeL/6uzbCfakWuLVH imFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=LscJFjoJLVax370bbjjUkdBy9lfnLd5L4hR3aqcqMxs=; b=AT0hnL74pFK7jDsgeavC0B4/p/XsSmWCylp86hdk09SGGAVPpIJKnSYW+HM4ImNYTm ZSBEjqhMH5qm0O21MqjoXJfQq4DCmxFYa4wbh4Y2WCVbJNk83LggZOowcrH7qAXVWCjA T9W6n23OtcRva+lE2Ivrid/3g9S9rmXfMf+46BR8GzE7LzsiEEX7ZwPOQk2DGPgMvQ5V RRK0yQfA4Et/t6RWwERD+8MhzJL3hANkgcsDPcI5jUcCEj/LNvx4DInze3G7NKVLwd7x cDp62llqHswNO5G6r7PK5js7U9GeBEArZMR8ErlLzWYUYWZut+15CrhJIiQtc7rLwRlv KBvQ== X-Gm-Message-State: AOAM531J8BnAIpwR7duJZJE7+vLWi87n2QIZcaQz3wB9qYyrT4rHyszU adt5jDTRkaDE/e5PVo3AAG6mNwMp3S76xDM/ X-Google-Smtp-Source: ABdhPJwzgPTE7ULrW+99l185z6FAhKICh/xtuRH7sRk/qJVb4hSzj455QPw9m3FHqWfqtOU6n1JLrXcnSLJT+Smj X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:a1c:e345:: with SMTP id a66mr16954306wmh.188.1604333083509; Mon, 02 Nov 2020 08:04:43 -0800 (PST) Date: Mon, 2 Nov 2020 17:03:47 +0100 In-Reply-To: Message-Id: Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v7 07/41] arm64: mte: Convert gcr_user into an exclude mask From: Andrey Konovalov To: Catalin Marinas , Will Deacon Cc: Vincenzo Frascino , kasan-dev@googlegroups.com, Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrey Konovalov X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Vincenzo Frascino The gcr_user mask is a per thread mask that represents the tags that are excluded from random generation when the Memory Tagging Extension is present and an 'irg' instruction is invoked. gcr_user affects the behavior on EL0 only. Currently that mask is an include mask and it is controlled by the user via prctl() while GCR_EL1 accepts an exclude mask. Convert the include mask into an exclude one to make it easier the register setting. Note: This change will affect gcr_kernel (for EL1) introduced with a future patch. Signed-off-by: Vincenzo Frascino Signed-off-by: Andrey Konovalov Reviewed-by: Catalin Marinas --- Change-Id: Id15c0b47582fb51594bb26fb8353d78c7d0953c1 --- arch/arm64/include/asm/processor.h | 2 +- arch/arm64/kernel/mte.c | 29 +++++++++++++++-------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index fce8cbecd6bc..e8cfc41a92d4 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -154,7 +154,7 @@ struct thread_struct { #endif #ifdef CONFIG_ARM64_MTE u64 sctlr_tcf0; - u64 gcr_user_incl; + u64 gcr_user_excl; #endif }; diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 06ba6c923ab7..a9f03be75cef 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -141,23 +141,22 @@ static void set_sctlr_el1_tcf0(u64 tcf0) preempt_enable(); } -static void update_gcr_el1_excl(u64 incl) +static void update_gcr_el1_excl(u64 excl) { - u64 excl = ~incl & SYS_GCR_EL1_EXCL_MASK; /* - * Note that 'incl' is an include mask (controlled by the user via - * prctl()) while GCR_EL1 accepts an exclude mask. + * Note that the mask controlled by the user via prctl() is an + * include while GCR_EL1 accepts an exclude mask. * No need for ISB since this only affects EL0 currently, implicit * with ERET. */ sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); } -static void set_gcr_el1_excl(u64 incl) +static void set_gcr_el1_excl(u64 excl) { - current->thread.gcr_user_incl = incl; - update_gcr_el1_excl(incl); + current->thread.gcr_user_excl = excl; + update_gcr_el1_excl(excl); } void flush_mte_state(void) @@ -172,7 +171,7 @@ void flush_mte_state(void) /* disable tag checking */ set_sctlr_el1_tcf0(SCTLR_EL1_TCF0_NONE); /* reset tag generation mask */ - set_gcr_el1_excl(0); + set_gcr_el1_excl(SYS_GCR_EL1_EXCL_MASK); } void mte_thread_switch(struct task_struct *next) @@ -183,7 +182,7 @@ void mte_thread_switch(struct task_struct *next) /* avoid expensive SCTLR_EL1 accesses if no change */ if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); - update_gcr_el1_excl(next->thread.gcr_user_incl); + update_gcr_el1_excl(next->thread.gcr_user_excl); } void mte_suspend_exit(void) @@ -191,13 +190,14 @@ void mte_suspend_exit(void) if (!system_supports_mte()) return; - update_gcr_el1_excl(current->thread.gcr_user_incl); + update_gcr_el1_excl(current->thread.gcr_user_excl); } long set_mte_ctrl(struct task_struct *task, unsigned long arg) { u64 tcf0; - u64 gcr_incl = (arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT; + u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & + SYS_GCR_EL1_EXCL_MASK; if (!system_supports_mte()) return 0; @@ -218,10 +218,10 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) if (task != current) { task->thread.sctlr_tcf0 = tcf0; - task->thread.gcr_user_incl = gcr_incl; + task->thread.gcr_user_excl = gcr_excl; } else { set_sctlr_el1_tcf0(tcf0); - set_gcr_el1_excl(gcr_incl); + set_gcr_el1_excl(gcr_excl); } return 0; @@ -230,11 +230,12 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) long get_mte_ctrl(struct task_struct *task) { unsigned long ret; + u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK; if (!system_supports_mte()) return 0; - ret = task->thread.gcr_user_incl << PR_MTE_TAG_SHIFT; + ret = incl << PR_MTE_TAG_SHIFT; switch (task->thread.sctlr_tcf0) { case SCTLR_EL1_TCF0_NONE: