diff mbox series

[RFC,v2,12/20] powerpc/64e: Remove unneeded #ifdef CONFIG_PPC_E500

Message ID f70e5249b9e6a9a06e6575aa0efbaf8ba93c3659.1715971869.git.christophe.leroy@csgroup.eu (mailing list archive)
State New
Headers show
Series Reimplement huge pages without hugepd on powerpc (8xx, e500, book3s/64) | expand

Commit Message

Christophe Leroy May 17, 2024, 7 p.m. UTC 
When it is a nohash/64 it can't be anything else than
CONFIG_PPC_E500 so remove the #ifdef as they are always true.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
 arch/powerpc/mm/nohash/tlb.c | 13 -------------
 1 file changed, 13 deletions(-)

Comments

Michael Ellerman May 24, 2024, 7:31 a.m. UTC | #1 
Christophe Leroy <christophe.leroy@csgroup.eu> writes:
> When it is a nohash/64 it can't be anything else than
> CONFIG_PPC_E500 so remove the #ifdef as they are always true.

I have a series doing some similar cleanups, I'll post it. We can decide
whether to merge it before your series or combine them or whatever.

cheers
Christophe Leroy May 24, 2024, 8:45 a.m. UTC | #2 
Le 24/05/2024 à 09:31, Michael Ellerman a écrit :
> Christophe Leroy <christophe.leroy@csgroup.eu> writes:
>> When it is a nohash/64 it can't be anything else than
>> CONFIG_PPC_E500 so remove the #ifdef as they are always true.
> 
> I have a series doing some similar cleanups, I'll post it. We can decide
> whether to merge it before your series or combine them or whatever.
> 

Great. I'll apply my series on top.

Note that it doesn't apply cleanly on merge branch (47279113c5d0), a 
3-way merge is needed:

$ LANG= git am -3 
~/Téléchargements/1-6-powerpc-64e-Remove-unused-IBM-HTW-code.patch
Applying: powerpc/64e: Remove unused IBM HTW code
Applying: powerpc/64e: Split out nohash Book3E 64-bit code
Using index info to reconstruct a base tree...
M	arch/powerpc/mm/nohash/Makefile
.git/rebase-apply/patch:554: trailing whitespace.
			def->shift = 0;	
warning: 1 line adds whitespace errors.
Falling back to patching base and 3-way merge...
Auto-merging arch/powerpc/mm/nohash/Makefile
Applying: powerpc/64e: Drop E500 ifdefs in 64-bit code
Applying: powerpc/64e: Drop MMU_FTR_TYPE_FSL_E checks in 64-bit code
Applying: powerpc/64e: Consolidate TLB miss handler patching
Applying: powerpc/64e: Drop unused TLB miss handlers

Thanks
Christophe
diff mbox series

Patch

diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c
index 5ffa0af4328a..d16f1ef7516c 100644
--- a/arch/powerpc/mm/nohash/tlb.c
+++ b/arch/powerpc/mm/nohash/tlb.c
@@ -403,8 +403,6 @@  static void __init setup_page_sizes(void)
 	unsigned int tlb0ps;
 	unsigned int eptcfg;
 	int i, psize;
-
-#ifdef CONFIG_PPC_E500
 	unsigned int mmucfg = mfspr(SPRN_MMUCFG);
 	int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
 
@@ -470,7 +468,6 @@  static void __init setup_page_sizes(void)
 
 		goto out;
 	}
-#endif
 
 	tlb0cfg = mfspr(SPRN_TLB0CFG);
 	tlb0ps = mfspr(SPRN_TLB0PS);
@@ -547,13 +544,11 @@  static void __init setup_mmu_htw(void)
 		patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
 		patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
 		break;
-#ifdef CONFIG_PPC_E500
 	case PPC_HTW_E6500:
 		extlb_level_exc = EX_TLB_SIZE;
 		patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
 		patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
 		break;
-#endif
 	}
 	pr_info("MMU: Book3E HW tablewalk %s\n",
 		book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
@@ -590,7 +585,6 @@  static void early_init_this_mmu(void)
 	}
 	mtspr(SPRN_MAS4, mas4);
 
-#ifdef CONFIG_PPC_E500
 	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 		unsigned int num_cams;
 		bool map = true;
@@ -611,7 +605,6 @@  static void early_init_this_mmu(void)
 			linear_map_top = map_mem_in_cams(linear_map_top,
 							 num_cams, false, true);
 	}
-#endif
 
 	/* A sync won't hurt us after mucking around with
 	 * the MMU configuration
@@ -643,7 +636,6 @@  static void __init early_init_mmu_global(void)
 	/* Look for HW tablewalk support */
 	setup_mmu_htw();
 
-#ifdef CONFIG_PPC_E500
 	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 		if (book3e_htw_mode == PPC_HTW_NONE) {
 			extlb_level_exc = EX_TLB_SIZE;
@@ -652,7 +644,6 @@  static void __init early_init_mmu_global(void)
 				exc_instruction_tlb_miss_bolted_book3e);
 		}
 	}
-#endif
 
 	/* Set the global containing the top of the linear mapping
 	 * for use by the TLB miss code
@@ -664,7 +655,6 @@  static void __init early_init_mmu_global(void)
 
 static void __init early_mmu_set_memory_limit(void)
 {
-#ifdef CONFIG_PPC_E500
 	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 		/*
 		 * Limit memory so we dont have linear faults.
@@ -675,7 +665,6 @@  static void __init early_mmu_set_memory_limit(void)
 		 */
 		memblock_enforce_memory_limit(linear_map_top);
 	}
-#endif
 
 	memblock_set_current_limit(linear_map_top);
 }
@@ -713,7 +702,6 @@  void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 	 * We crop it to the size of the first MEMBLOCK to
 	 * avoid going over total available memory just in case...
 	 */
-#ifdef CONFIG_PPC_E500
 	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 		unsigned long linear_sz;
 		unsigned int num_cams;
@@ -726,7 +714,6 @@  void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 
 		ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
 	} else
-#endif
 		ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
 
 	/* Finally limit subsequent allocations */