Message ID | fd759cce9818d0627c97210bf492fa892eb244b4.1666824663.git.kai.huang@intel.com (mailing list archive) |
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State | New |
Headers | show
Return-Path: <owner-linux-mm@kvack.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5622C38A2D for <linux-mm@archiver.kernel.org>; Wed, 26 Oct 2022 23:18:24 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 465778E0010; Wed, 26 Oct 2022 19:18:24 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 415668E0001; Wed, 26 Oct 2022 19:18:24 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 2DCBA8E0010; Wed, 26 Oct 2022 19:18:24 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 1E5AF8E0001 for <linux-mm@kvack.org>; Wed, 26 Oct 2022 19:18:24 -0400 (EDT) Received: from smtpin26.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay07.hostedemail.com (Postfix) with ESMTP id EDE121605C1 for <linux-mm@kvack.org>; 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26 Oct 2022 16:18:22 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="737446567" X-IronPort-AV: E=Sophos;i="5.95,215,1661842800"; d="scan'208";a="737446567" Received: from fordon1x-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.24.177]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 16:18:19 -0700 From: Kai Huang <kai.huang@intel.com> To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, seanjc@google.com, pbonzini@redhat.com, dave.hansen@intel.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, peterz@infradead.org, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v6 20/21] x86/virt/tdx: Flush cache in kexec() when TDX is enabled Date: Thu, 27 Oct 2022 12:16:19 +1300 Message-Id: <fd759cce9818d0627c97210bf492fa892eb244b4.1666824663.git.kai.huang@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <cover.1666824663.git.kai.huang@intel.com> References: <cover.1666824663.git.kai.huang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ARC-Authentication-Results: i=1; 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Series |
TDX host kernel support
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expand
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diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index c21b7347a26d..a8f482c6e600 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -765,8 +765,15 @@ void __noreturn stop_this_cpu(void *dummy) * * Test the CPUID bit directly because the machine might've cleared * X86_FEATURE_SME due to cmdline options. + * + * Similar to SME, if the TDX module is ever initialized, the + * cachelines associated with any TDX private KeyID must be + * flushed before transiting to the new kernel. The TDX module + * is initialized on demand, and it takes the mutex to read it's + * status. Just check whether TDX is enabled by BIOS instead to + * flush cache. */ - if (cpuid_eax(0x8000001f) & BIT(0)) + if (cpuid_eax(0x8000001f) & BIT(0) || platform_tdx_enabled()) native_wbinvd(); for (;;) { /*