From patchwork Wed Mar 26 11:31:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3892861 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2253ABF549 for ; Wed, 26 Mar 2014 11:31:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35ECD2011B for ; Wed, 26 Mar 2014 11:31:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3852320172 for ; Wed, 26 Mar 2014 11:31:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753961AbaCZLb0 (ORCPT ); Wed, 26 Mar 2014 07:31:26 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:48395 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751614AbaCZLbZ (ORCPT ); Wed, 26 Mar 2014 07:31:25 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N31005K7K0B9T00@mailout2.samsung.com>; Wed, 26 Mar 2014 20:31:23 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.49]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id A6.26.10092.B8AB2335; Wed, 26 Mar 2014 20:31:23 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-36-5332ba8bdf6d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id F7.7E.28157.B8AB2335; Wed, 26 Mar 2014 20:31:23 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N31009LVK0BQ760@mmp2.samsung.com>; Wed, 26 Mar 2014 20:31:23 +0900 (KST) From: Seungwon Jeon To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Kukjin Kim' , 'Jaehoon Chung' , 'Ulf Hansson' , 'Alim Akhtar' References: In-reply-to: Subject: [PATCH v2 3/7] mmc: dw_mmc: exynos: move definitions to header file Date: Wed, 26 Mar 2014 20:31:22 +0900 Message-id: <000301cf48e6$ea205860$be610920$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac9FDjtZo1aMTMCOStGdx+bxiO4TmwD1P6hw Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBIsWRmVeSWpSXmKPExsVy+t8zQ93uXUbBBq1TdSwezNvGZjHh8nZG ixu/2lgtehdcZbM48r+f0WLG+X1MFsfXhjuwe9y5tofN48arhUwefVtWMXp83iQXwBLFZZOS mpNZllqkb5fAlXHgSQtbwWT1itUHrjM3ME5U7GLk5JAQMJH492QpG4QtJnHh3nogm4tDSGAZ o8TK7bOYYYr+3FoKlZjOKHFv92J2COcPo8SM1z9YQKrYBLQk/r55A9YhIuAg8e76BSYQm1ng BKPEvMXGXYwcQA3cEqubg0DCnAI8Euv+dDKDhIUFfCRm7GEFCbMIqEocfA7RyStgK3Hl41ZG CFtQ4sfkeywg5cwC6hJTpuRCDJeX2LzmLdgUCaDwo7+6EPuNJNobJjJDlIhI7HvxjhHkYAmB e+wSj79dZ4RYJSDxbfIhFoheWYlNB6C+lZQ4uOIGywRGiVlIFs9CWDwLyeJZSDYsYGRZxSia WpBcUJyUXmSsV5yYW1yal66XnJ+7iRESq/07GO8esD7EmAy0fSKzlGhyPjDW80riDY3NjCxM TUyNjcwtzUgTVhLnvf8wKUhIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QD4yE1uavur9d/nH3J Wjnp/gLPg1aRO+4qHndaYuIRXT35sTwXV5LnFgkrh5066W3v1nO4/75ZlDBh0qUv3E/qWO+x bP54ftpJDW9Pk5TJ8+YF1V/alSXActcvTsl5w+F3IkqPfQqUe7fG9GosW9shpbOwJaG6dM+P 5NQpO79PFwyrmx2fmv3zhRJLcUaioRZzUXEiAGP2nivrAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKKsWRmVeSWpSXmKPExsVy+t9jQd3uXUbBBq/vq1s8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWqgdEm IzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB+gCJYWyxJxS oFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhHWPGgSctbAWT1StWH7jO3MA4UbGLkZND QsBE4s+tpWwQtpjEhXvrgWwuDiGB6YwS93YvZodw/jBKzHj9gwWkik1AS+LvmzfMILaIgIPE u+sXmEBsZoETjBLzFht3MXIANXBLrG4OAglzCvBIrPvTyQwSFhbwkZixhxUkzCKgKnHwOUQn r4CtxJWPWxkhbEGJH5PvsYCUMwuoS0yZkgsxXF5i85q3YFMkgMKP/upC7DeSaG+YyAxRIiKx 78U7xgmMQrOQDJqFMGgWkkGzkHQsYGRZxSiaWpBcUJyUnmukV5yYW1yal66XnJ+7iRGcCJ5J 72Bc1WBxiFGAg1GJh9eizzBYiDWxrLgy9xCjBAezkgjvjrVGwUK8KYmVValF+fFFpTmpxYcY k4HenMgsJZqcD0xSeSXxhsYmZkaWRmYWRibm5qQJK4nzHmy1DhQSSE8sSc1OTS1ILYLZwsTB KdXA6PSgQyxZX6WjXuLamWDN3VK2LotVHa+bf56zIXt964q2l2pTu8yM+86XLFlpuPpr6cnd ca6brQrdpC9vncvVf0dhrauy28E9n9a0v+7LqJZgOfBwpfWtlIcxJWtY2e4nc8o7dKhpVmaJ ihiLxGVZLJ/3f/o+aV2T/0lnTjr/Sitla9RWaXNRYinOSDTUYi4qTgQAdtevM0gDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move some parts related to definition to header file. Signed-off-by: Seungwon Jeon Acked-by: Jaehoon Chung --- drivers/mmc/host/dw_mmc-exynos.c | 46 ++++--------------------------- drivers/mmc/host/dw_mmc-exynos.h | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 40 deletions(-) create mode 100644 drivers/mmc/host/dw_mmc-exynos.h diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index a2d06c5..bab97e9 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -21,42 +21,8 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#include "dw_mmc-exynos.h" -#define NUM_PINS(x) (x + 2) - -#define SDMMC_CLKSEL 0x09C -#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) -#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) -#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) -#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) -#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ - SDMMC_CLKSEL_CCLK_DRIVE(y) | \ - SDMMC_CLKSEL_CCLK_DIVIDER(z)) -#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) - -#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 -#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 - -/* Block number in eMMC */ -#define DWMCI_BLOCK_NUM 0xFFFFFFFF - -#define SDMMC_EMMCP_BASE 0x1000 -#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) -#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) -#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) -#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) - -/* SMU control bits */ -#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) -#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) -#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) -#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) -#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) -#define DWMCI_MPSCTRL_ECB_MODE BIT(2) -#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) -#define DWMCI_MPSCTRL_VALID BIT(0) - -#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */ /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { @@ -104,11 +70,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) { mci_writel(host, MPSBEGIN0, 0); - mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); - mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT | - DWMCI_MPSCTRL_NON_SECURE_READ_BIT | - DWMCI_MPSCTRL_VALID | - DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); + mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | + SDMMC_MPSCTRL_NON_SECURE_READ_BIT | + SDMMC_MPSCTRL_VALID | + SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); } return 0; diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h new file mode 100644 index 0000000..2554e2f --- /dev/null +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -0,0 +1,55 @@ +/* + * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver + * + * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _DW_MMC_EXYNOS_H_ +#define _DW_MMC_EXYNOS_H_ + +/* Extended Register's Offset */ +#define SDMMC_CLKSEL 0x09C + +/* CLKSEL register defines */ +#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) +#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) +#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) +#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) +#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ + SDMMC_CLKSEL_CCLK_DRIVE(y) | \ + SDMMC_CLKSEL_CCLK_DIVIDER(z)) +#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) + +/* Protector Register */ +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control defines */ +#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) +#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) +#define SDMMC_MPSCTRL_ECB_MODE BIT(2) +#define SDMMC_MPSCTRL_ENCRYPTION BIT(1) +#define SDMMC_MPSCTRL_VALID BIT(0) + +/* Maximum number of Ending sector */ +#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF + +/* Fixed clock divider */ +#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 +#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 + +/* Minimal required clock frequency for cclkin, unit: HZ */ +#define EXYNOS_CCLKIN_MIN 50000000 + +#endif /* _DW_MMC_EXYNOS_H_ */