From patchwork Wed Mar 26 11:31:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3892871 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B850ABF540 for ; Wed, 26 Mar 2014 11:31:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C34F220222 for ; Wed, 26 Mar 2014 11:31:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B277D20172 for ; Wed, 26 Mar 2014 11:31:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754122AbaCZLbi (ORCPT ); Wed, 26 Mar 2014 07:31:38 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:65108 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751614AbaCZLbh (ORCPT ); Wed, 26 Mar 2014 07:31:37 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N3100E75K0OBO20@mailout3.samsung.com>; Wed, 26 Mar 2014 20:31:36 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.48]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id A4.1E.10364.79AB2335; Wed, 26 Mar 2014 20:31:36 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-42-5332ba9704d2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id BE.4E.29263.79AB2335; Wed, 26 Mar 2014 20:31:35 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N31002N4K0NDK60@mmp1.samsung.com>; Wed, 26 Mar 2014 20:31:35 +0900 (KST) From: Seungwon Jeon To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Kukjin Kim' , 'Jaehoon Chung' , 'Ulf Hansson' , 'Alim Akhtar' References: In-reply-to: Subject: [PATCH v2 4/7] mmc: dw_mmc: exynos: incorporate ciu_div into timing property Date: Wed, 26 Mar 2014 20:31:34 +0900 Message-id: <000401cf48e6$f173a680$d45af380$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac9FDjtZo1aMTMCOStGdx+bxiO4TmwD1P6hw Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKIsWRmVeSWpSXmKPExsVy+t8zA90Zu4yCDd52Mlk8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWKyyYl NSezLLVI3y6BK+PtzeNMBau1KhbPmMLewHhTqYuRk0NCwERi95R+JghbTOLCvfVsILaQwDJG iUtnAmFqDq9rZ+9i5AKKL2KU6D0ymRnC+cMosfD7fLAONgEtib9v3jCD2CICDhLvrl8Am8os cIJRYt5i4y5GDqAGbonVzUEgYU4BHol1fzqZQcLCAuES3757goRZBFQlWh8+ZAEJ8wrYStze GAoS5hUQlPgx+R5YmFlAXWLKlFyI2fISm9e8BRsiARR+9FcXYr2RRHvDRGaIEhGJfS/eMUI8 8pJd4vUSFYhFAhLfJh9igWiVldh0gBmiRFLi4IobLBMYJWYh2TsLYe8sJHtnIVmwgJFlFaNo akFyQXFSepGJXnFibnFpXrpecn7uJkZIlE7YwXjvgPUhxmSg7ROZpUST84FRnlcSb2hsZmRh amJqbGRuaUaasJI4r9qjpCAhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjBZhDBzL39/aWxnr e67g8TpRVq9JVde95dODJzCs04y8cn+jpWoQ94l773kFJp0//ERN6QW31fPQV8sTjN2dvDY6 7vu3+FiOilEr27nl2/ZkLOIXU44TluowilsQL9fHNL/kheyrpk2bjr7nSlzifuDQheD82uun u/Kdtido3zl8vqniMOuqCUosxRmJhlrMRcWJAJuLTj7oAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCKsWRmVeSWpSXmKPExsVy+t9jAd3pu4yCDdqmWFk8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWqgdEm IzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB+gCJYWyxJxS oFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhHWPG25vHmQpWa1UsnjGFvYHxplIXIyeH hICJxOF17ewQtpjEhXvr2boYuTiEBBYxSvQemcwM4fxhlFj4fT4bSBWbgJbE3zdvmEFsEQEH iXfXLzCB2MwCJxgl5i027mLkAGrglljdHAQS5hTgkVj3p5MZJCwsEC7x7bsnSJhFQFWi9eFD FpAwr4CtxO2NoSBhXgFBiR+T74GFmQXUJaZMyYWYLS+xec1bsCESQOFHf3Uh1htJtDdMZIYo EZHY9+Id4wRGoVlIBs1CGDQLyaBZSDoWMLKsYhRNLUguKE5KzzXUK07MLS7NS9dLzs/dxAhO A8+kdjCubLA4xCjAwajEwzthgmGwEGtiWXFl7iFGCQ5mJRHeHWuNgoV4UxIrq1KL8uOLSnNS iw8xJgN9OZFZSjQ5H5ii8kriDY1NzIwsjcwsjEzMzUkTVhLnPdBqHSgkkJ5YkpqdmlqQWgSz hYmDU6qBkaen9Mek7Q/NV+3eskn8pnbvzCWrCvIL/287n2B/4ukqC/XAp5tCPqW2mIqfXnTj vgFH+7rsNMF/op6nI1NlJHcJfr+0UqnL3Tfh/IXIi5clDto/iN/Z/DXnzuGbJ7rm/1r9+NxJ NmHr01dzVV9NVr8Vkrj1/J7OLVqlHns3vD4tWn3iX3xnjZISS3FGoqEWc1FxIgCmqkM4RwMA AA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ciu_div may not be common value for all speed mode. So, it needs to be attached to CLKSEL timing. Signed-off-by: Seungwon Jeon --- drivers/mmc/host/dw_mmc-exynos.c | 75 ++++++++++++++++++++++++++------------ drivers/mmc/host/dw_mmc-exynos.h | 1 + 2 files changed, 53 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index bab97e9..39f9114 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -39,6 +39,7 @@ struct dw_mci_exynos_priv_data { u8 ciu_div; u32 sdr_timing; u32 ddr_timing; + u32 hs200_timing; u32 cur_speed; }; @@ -64,6 +65,18 @@ static struct dw_mci_exynos_compatible { }, }; +static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) +{ + struct dw_mci_exynos_priv_data *priv = host->priv; + + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) + return EXYNOS4412_FIXED_CIU_CLK_DIV; + else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) + return EXYNOS4210_FIXED_CIU_CLK_DIV; + else + return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; +} + static int dw_mci_exynos_priv_init(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; @@ -77,6 +90,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); } + priv->ciu_div = dw_mci_exynos_get_ciu_div(host); + return 0; } @@ -84,7 +99,7 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; - host->bus_hz /= (priv->ciu_div + 1); + host->bus_hz /= priv->ciu_div; return 0; } @@ -151,9 +166,10 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) struct dw_mci_exynos_priv_data *priv = host->priv; unsigned int wanted = ios->clock; unsigned long actual; - u8 div = priv->ciu_div + 1; - if (ios->timing == MMC_TIMING_MMC_DDR52) { + if (ios->timing == MMC_TIMING_MMC_HS200) { + mci_writel(host, CLKSEL, priv->hs200_timing); + } else if (ios->timing == MMC_TIMING_MMC_DDR52) { mci_writel(host, CLKSEL, priv->ddr_timing); /* Should be double rate for DDR mode */ if (ios->bus_width == MMC_BUS_WIDTH_8) @@ -174,6 +190,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) wanted = EXYNOS_CCLKIN_MIN; if (wanted != priv->cur_speed) { + u8 div = dw_mci_exynos_get_ciu_div(host); int ret = clk_set_rate(host->ciu_clk, wanted * div); if (ret) dev_warn(host->dev, @@ -186,14 +203,34 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) } } +static int dw_mci_exynos_dt_populate_timing(struct dw_mci *host, + unsigned int ctrl_type, + const char *propname, + u32 *out_values) +{ + struct device_node *np = host->dev->of_node; + u32 timing[3]; + int ret; + + ret = of_property_read_u32_array(np, propname, timing, 3); + if (ret) + return ret; + + if (ctrl_type == DW_MCI_TYPE_EXYNOS4412 || + ctrl_type == DW_MCI_TYPE_EXYNOS4210) + timing[2] = 0; + + *out_values = SDMMC_CLKSEL_TIMING(timing[0], timing[1], timing[2]); + + return 0; +} + + static int dw_mci_exynos_parse_dt(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv; struct device_node *np = host->dev->of_node; - u32 timing[2]; - u32 div = 0; - int idx; - int ret; + int idx, ret; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) { @@ -206,29 +243,21 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host) priv->ctrl_type = exynos_compat[idx].ctrl_type; } - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) - priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; - else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) - priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; - else { - of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); - priv->ciu_div = div; - } - - ret = of_property_read_u32_array(np, - "samsung,dw-mshc-sdr-timing", timing, 2); + ret = dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-sdr-timing", &priv->sdr_timing); if (ret) return ret; - priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); - - ret = of_property_read_u32_array(np, - "samsung,dw-mshc-ddr-timing", timing, 2); + ret = dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-ddr-timing", &priv->ddr_timing); if (ret) return ret; - priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); + dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-hs200-timing", &priv->hs200_timing); + host->priv = priv; + return 0; } diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index 2554e2f..2c8c228 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -20,6 +20,7 @@ #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) +#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7) #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z))