From patchwork Fri Aug 30 15:13:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 2852121 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 77B019F2F4 for ; Fri, 30 Aug 2013 15:13:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 38ACB20182 for ; Fri, 30 Aug 2013 15:13:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C752320488 for ; Fri, 30 Aug 2013 15:13:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756561Ab3H3PNo (ORCPT ); Fri, 30 Aug 2013 11:13:44 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:46336 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756321Ab3H3PNn (ORCPT ); Fri, 30 Aug 2013 11:13:43 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSC00818NMR7JJ0@mailout3.samsung.com> for linux-mmc@vger.kernel.org; Sat, 31 Aug 2013 00:13:42 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id B5.2D.29948.6A6B0225; Sat, 31 Aug 2013 00:13:42 +0900 (KST) X-AuditID: cbfee691-b7f4a6d0000074fc-09-5220b6a66fd2 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 38.FB.05832.6A6B0225; Sat, 31 Aug 2013 00:13:42 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MSC00DTTNMU6520@mmp2.samsung.com>; Sat, 31 Aug 2013 00:13:42 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Jaehoon Chung' References: In-reply-to: Subject: [PATCH 15/22] mmc: dw_mmc: adjust the fifoth with block size Date: Sat, 31 Aug 2013 00:13:42 +0900 Message-id: <001201cea593$8358e620$8a0ab260$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac03z3aCvVFr8FaITt2vKVQKst76fw3OcIrwS9fJ1BAByUIdcA== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t8zY91l2xSCDDY3K1lsf72RzeLGrzZW iyP/+xkdmD0OXVnL6NG3ZRWjx+dNcgHMUVw2Kak5mWWpRfp2CVwZSx6YFhxTq9j+4SpjA+Nl uS5GTg4JAROJTS/OskHYYhIX7q0Hsrk4hASWMUrsX7mREabo48UJLBCJ6YwSPy9vYwZJCAn8 YZS40xUCYrMJaEn8ffMGLC4iICvx888FsKnMAt4Sr+avARrEAVTPLbG6OQgkzCnAI7HuTydY ubCAq8SiOZ1g5SwCqhI3301gBbF5BWwlPhz/xQhhC0r8mHyPBWQMs4C6xJQpuRDT5SU2r3nL DBKWAAo/+qsLcYCTxNmmg4wQJSIS+168YwS5XkJgH7vE7jVrmCBWCUh8m3yIBaJXVmLTAWaI byUlDq64wTKBUWIWksWzEBbPQrJ4FpINCxhZVjGKphYkFxQnpReZ6hUn5haX5qXrJefnbmKE RN7EHYz3D1gfYkwG2j6RWUo0OR8YuXkl8YbGZkYWpiamxkbmlmakCSuJ86q3WAcKCaQnlqRm p6YWpBbFF5XmpBYfYmTi4JRqYFSN2f5Z0Vhi49PHGRaSqhMFVu09sOFM7kU21tIJcVI7NBk5 G8tufDyfrPvW7Y3xg8vp1k9fJi5qUr7nFf2zPKCCSf8Gr1udfphE6Zv8bf933d8x77pLgc6Z qX9c5mlLe1/Ospx0c+8EBtdoL9H2aImY3kvzA1O/HT401deWc1IES29/hdrtM0osxRmJhlrM RcWJAL9jQt/SAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsVy+t9jQd1l2xSCDC5MkLPY/nojm8WNX22s Fkf+9zM6MHscurKW0aNvyypGj8+b5AKYoxoYbTJSE1NSixRS85LzUzLz0m2VvIPjneNNzQwM dQ0tLcyVFPISc1NtlVx8AnTdMnOANikplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0Jgusx MkADCesYM5Y8MC04plax/cNVxgbGy3JdjJwcEgImEh8vTmCBsMUkLtxbz9bFyMUhJDCdUeLn 5W3MIAkhgT+MEne6QkBsNgEtib9v3oDFRQRkJX7+ucAGYjMLeEu8mr+GsYuRA6ieW2J1cxBI mFOAR2Ldn06wcmEBV4lFczrBylkEVCVuvpvACmLzCthKfDj+ixHCFpT4MfkeC8gYZgF1iSlT ciGmy0tsXvOWGSQsARR+9FcX4gAnibNNBxkhSkQk9r14xziBUWgWkkGzEAbNQjJoFpKOBYws qxhFUwuSC4qT0nON9IoTc4tL89L1kvNzNzGC4/qZ9A7GVQ0WhxgFOBiVeHh3LlcIEmJNLCuu zD3EKMHBrCTC+3ExUIg3JbGyKrUoP76oNCe1+BBjMtCbE5mlRJPzgSknryTe0NjEzMjSyMzC yMTcnDRhJXHeg63WgUIC6YklqdmpqQWpRTBbmDg4pRoYZZPdjqScZTpgM1/60feNX+W67r5W vXvyIX9qzsZ1Elr7zlxatkqg3n7XLP7lV5f3LJO99vfF1TMvWgwP6azyUnu3m1F18oE/ziyH el6GeG9znj5Z2EUxItT3cfhX8V/5be+n8LA/mlRVvnKFrIpXp4Wshc0a51glpdrjM+fNW9x9 4u3m+ZmvuZRYijMSDbWYi4oTAZakToUvAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change helps to choose msize, rx_watermark and tx_watermak depending on block size for IDMAC mode. For SDIO block size can be variable, so if these values are set incorrectly, card clock may stop. Signed-off-by: Seungwon Jeon Tested-by: Alim Akhtar --- drivers/mmc/host/dw_mmc.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- drivers/mmc/host/dw_mmc.h | 4 ++ include/linux/mmc/dw_mmc.h | 1 + 3 files changed, 76 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 29deeba..ac4abf9 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -529,6 +529,47 @@ static void dw_mci_post_req(struct mmc_host *mmc, data->host_cookie = 0; } +static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) +{ +#ifdef CONFIG_MMC_DW_IDMAC + unsigned int blksz = data->blksz; + const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; + u32 fifo_width = 1 << host->data_shift; + u32 blksz_depth = blksz / fifo_width, fifoth_val; + u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; + int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; + + tx_wmark = (host->fifo_depth) / 2; + tx_wmark_invers = host->fifo_depth - tx_wmark; + + /* + * MSIZE is '1', + * if blksz is not a multiple of the FIFO width + */ + if (blksz % fifo_width) { + msize = 0; + rx_wmark = 1; + goto done; + } + + do { + if (!((blksz_depth % mszs[idx]) || + (tx_wmark_invers % mszs[idx]))) { + msize = idx; + rx_wmark = mszs[idx] - 1; + break; + } + } while (--idx > 0); + /* + * If idx is '0', it won't be tried + * Thus, initial values are uesed + */ +done: + fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); + mci_writel(host, FIFOTH, fifoth_val); +#endif +} + static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) { int sg_len; @@ -553,6 +594,14 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, sg_len); + /* + * Decide the MSIZE and RX/TX Watermark. + * If current block size is same with previous size, + * no need to update fifoth. + */ + if (host->prev_blksz != data->blksz) + dw_mci_adjust_fifoth(host, data); + /* Enable the DMA interface */ temp = mci_readl(host, CTRL); temp |= SDMMC_CTRL_DMA_ENABLE; @@ -603,6 +652,21 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) temp = mci_readl(host, CTRL); temp &= ~SDMMC_CTRL_DMA_ENABLE; mci_writel(host, CTRL, temp); + + /* + * Use the initial fifoth_val for PIO mode. + * If next issued data may be transfered by DMA mode, + * prev_blksz should be invalidated. + */ + mci_writel(host, FIFOTH, host->fifoth_val); + host->prev_blksz = 0; + } else { + /* + * Keep the current block size. + * It will be used to decide whether to update + * fifoth register next time. + */ + host->prev_blksz = data->blksz; } } @@ -2368,8 +2432,8 @@ int dw_mci_probe(struct dw_mci *host) fifo_size = host->pdata->fifo_depth; } host->fifo_depth = fifo_size; - host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | - ((fifo_size/2) << 0)); + host->fifoth_val = + SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); mci_writel(host, FIFOTH, host->fifoth_val); /* disable clock to CIU */ @@ -2552,8 +2616,12 @@ int dw_mci_resume(struct dw_mci *host) if (host->use_dma && host->dma_ops->init) host->dma_ops->init(host); - /* Restore the old value at FIFOTH register */ + /* + * Restore the initial value at FIFOTH register + * And Invalidate the prev_blksz with zero + */ mci_writel(host, FIFOTH, host->fifoth_val); + host->prev_blksz = 0; /* Put in max timeout */ mci_writel(host, TMOUT, 0xFFFFFFFF); diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index b281fdc..a0f2f8d 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -128,6 +128,10 @@ #define SDMMC_CMD_INDX(n) ((n) & 0x1F) /* Status register defines */ #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) +/* FIFOTH register defines */ +#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ + ((r) & 0xFFF) << 16 | \ + ((t) & 0xFFF)) /* Internal DMAC interrupt defines */ #define SDMMC_IDMAC_INT_AI BIT(9) #define SDMMC_IDMAC_INT_NI BIT(8) diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h index 198f0fa..4ec9dcc 100644 --- a/include/linux/mmc/dw_mmc.h +++ b/include/linux/mmc/dw_mmc.h @@ -129,6 +129,7 @@ struct dw_mci { struct mmc_request *mrq; struct mmc_command *cmd; struct mmc_data *data; + unsigned int prev_blksz; struct workqueue_struct *card_workqueue; /* DMA interface members*/