From patchwork Fri Mar 21 14:03:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3874571 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 58961BF549 for ; Fri, 21 Mar 2014 14:03:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 66C5120279 for ; Fri, 21 Mar 2014 14:03:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5ED742027D for ; Fri, 21 Mar 2014 14:03:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760951AbaCUODl (ORCPT ); Fri, 21 Mar 2014 10:03:41 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:45469 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760353AbaCUODk (ORCPT ); Fri, 21 Mar 2014 10:03:40 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2S003LEHQ3XI50@mailout1.samsung.com>; Fri, 21 Mar 2014 23:03:39 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 6F.B9.10364.BB64C235; Fri, 21 Mar 2014 23:03:39 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-cc-532c46bb2ea1 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 8F.37.28157.BB64C235; Fri, 21 Mar 2014 23:03:39 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N2S00D57HQ35C90@mmp2.samsung.com>; Fri, 21 Mar 2014 23:03:39 +0900 (KST) From: Seungwon Jeon To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Kukjin Kim' , 'Jaehoon Chung' , 'Ulf Hansson' , 'Alim Akhtar' Subject: [PATCH 3/7] mmc: dw_mmc: exynos: move definitions to header file Date: Fri, 21 Mar 2014 23:03:40 +0900 Message-id: <001d01cf450e$5c8ae960$15a0bc20$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac9FDlxmHEny1N07QmOqQ3M4JbMDZw== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t8zY93dbjrBBtcOK1k8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWKyyYl NSezLLVI3y6BK2Pv14uMBf3qFdNPTGFrYOxT7GLk5JAQMJGYur+VFcIWk7hwbz0biC0ksIxR 4ugqV5ia7VNeMHUxcgHFpzNKzHz+EKroD6PEiaNaIDabgJbE3zdvmEFsEQEHiXfXLzCB2MwC Jxgl5i02BrGFBTwlZt5+DbaMRUBVYs/nq2A1vAK2Es8+rmOFsAUlfky+x9LFyAHUqy4xZUou xBh5ic1r3jKDhCWAwo/+6kJs0pPYf+kWK0SJiMS+F+8YIU4+xS7xapU8xCYBiW+TD7FAtMpK bDrADFEiKXFwxQ2WCYxis5DsnYWwdxaSvbOQLFjAyLKKUTS1ILmgOCm9yESvODG3uDQvXS85 P3cTIyTyJuxgvHfA+hBjMtD2icxSosn5wMjNK4k3NDYzsjA1MTU2Mrc0I01YSZxX7VFSkJBA emJJanZqakFqUXxRaU5q8SFGJg5OqQZG7r49r2VP3b3yfEbymuNaScrNrzT4F29/6inBtNvL /u2/wx7GmdfWZN+zeVfFuzfX+kHRgcwT6kcM7n4/+kYufm6n7v6oHdr31jlcE9iiHen13yk5 TeNsDTPDiWT7O6c6pWbPniT1Zv0aybsvOW8a6df9UW1m/LtU/Ni2J3mTjh7R/WEXaqe2Woml OCPRUIu5qDgRAEXaycfSAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsVy+t9jQd3dbjrBBjPeylo8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWqgdEm IzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB+gCJYWyxJxS oFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhHWPG3q8XGQv61Sumn5jC1sDYp9jFyMkh IWAisX3KCyYIW0ziwr31bF2MXBxCAtMZJWY+f8gGkhAS+MMoceKoFojNJqAl8ffNG2YQW0TA QeLd9QtgzcwCJxgl5i02BrGFBTwlZt5+zQpiswioSuz5fBWshlfAVuLZx3WsELagxI/J91i6 GDmAetUlpkzJhRgjL7F5zVtmkLAEUPjRX12ITXoS+y/dYoUoEZHY9+Id4wRGgVlIBs1CGDQL yaBZSDoWMLKsYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiO7WfSOxhXNVgcYhTgYFTi4a3g 1A4WYk0sK67MPcQowcGsJMLbaacTLMSbklhZlVqUH19UmpNafIgxGejNicxSosn5wLSTVxJv aGxiZmRpZGZhZGJuTpqwkjjvwVbrQCGB9MSS1OzU1ILUIpgtTBycUg2M3TzWt/bosX86szrf V3/KcX2eUA6HoisujZxGFZFLlCt27vh8eN3608d+XYjp2bxPputF9S6zhw9jL5QYzk5bsPHq noa7zKfVVJ8nnNv+cXnMQd0sDs3MbiXb73qfwrszio4dFF3tyJzUU7ewdeqqtxoz3Ldv3ecp IfV8a94cNVMVo6L9UsH5SizFGYmGWsxFxYkAfED+fzEDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Moves some parts related to definition to header file Signed-off-by: Seungwon Jeon --- drivers/mmc/host/dw_mmc-exynos.c | 46 ++++--------------------------- drivers/mmc/host/dw_mmc-exynos.h | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 40 deletions(-) create mode 100644 drivers/mmc/host/dw_mmc-exynos.h diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 89aa019..801861b 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -21,42 +21,8 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#include "dw_mmc-exynos.h" -#define NUM_PINS(x) (x + 2) - -#define SDMMC_CLKSEL 0x09C -#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) -#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) -#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) -#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) -#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ - SDMMC_CLKSEL_CCLK_DRIVE(y) | \ - SDMMC_CLKSEL_CCLK_DIVIDER(z)) -#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) - -#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 -#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 - -/* Block number in eMMC */ -#define DWMCI_BLOCK_NUM 0xFFFFFFFF - -#define SDMMC_EMMCP_BASE 0x1000 -#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) -#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) -#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) -#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) - -/* SMU control bits */ -#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) -#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) -#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) -#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) -#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) -#define DWMCI_MPSCTRL_ECB_MODE BIT(2) -#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) -#define DWMCI_MPSCTRL_VALID BIT(0) - -#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */ /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { @@ -104,11 +70,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) { mci_writel(host, MPSBEGIN0, 0); - mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); - mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT | - DWMCI_MPSCTRL_NON_SECURE_READ_BIT | - DWMCI_MPSCTRL_VALID | - DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); + mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | + SDMMC_MPSCTRL_NON_SECURE_READ_BIT | + SDMMC_MPSCTRL_VALID | + SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); } return 0; diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h new file mode 100644 index 0000000..a4c6e10 --- /dev/null +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -0,0 +1,55 @@ +/* + * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver + * + * Copyright (C) 201333Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _DW_MMC_EXYNOS_H_ +#define _DW_MMC_EXYNOS_H_ + +/* Extended Register's Offset */ +#define SDMMC_CLKSEL 0x09C + +/* CLKSEL register defines */ +#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) +#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) +#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) +#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) +#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ + SDMMC_CLKSEL_CCLK_DRIVE(y) | \ + SDMMC_CLKSEL_CCLK_DIVIDER(z)) +#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) + +/* Protector Register */ +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control defines */ +#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) +#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) +#define SDMMC_MPSCTRL_ECB_MODE BIT(2) +#define SDMMC_MPSCTRL_ENCRYPTION BIT(1) +#define SDMMC_MPSCTRL_VALID BIT(0) + +/* Maximum number of Ending sector */ +#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF + +/* Fixed clock divider */ +#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 +#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 + +/* Minimal required clock frequency for cclkin, unit: HZ */ +#define EXYNOS_CCLKIN_MIN 50000000 + +#endif /* _DW_MMC_EXYNOS_H_ */