From patchwork Wed Jan 15 14:10:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3491941 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 226AD9F32F for ; Wed, 15 Jan 2014 14:10:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1C7F920121 for ; Wed, 15 Jan 2014 14:10:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A23D3200E9 for ; Wed, 15 Jan 2014 14:10:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751807AbaAOOKu (ORCPT ); Wed, 15 Jan 2014 09:10:50 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:56085 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751735AbaAOOKo (ORCPT ); Wed, 15 Jan 2014 09:10:44 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MZG00MP54PV5880@mailout1.samsung.com> for linux-mmc@vger.kernel.org; Wed, 15 Jan 2014 23:10:43 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.50]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id EF.9A.14803.3E696D25; Wed, 15 Jan 2014 23:10:43 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-45-52d696e3da5e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 1C.43.29263.3E696D25; Wed, 15 Jan 2014 23:10:43 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MZG00F9D4PV7F30@mmp2.samsung.com>; Wed, 15 Jan 2014 23:10:43 +0900 (KST) From: Seungwon Jeon To: 'Chris Ball' , 'Ulf Hansson' Cc: linux-mmc@vger.kernel.org References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> In-reply-to: Subject: [PATCH 1/7] mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Wed, 15 Jan 2014 23:10:43 +0900 Message-id: <001f01cf11fb$93d188c0$bb749a40$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22A= Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNIsWRmVeSWpSXmKPExsVy+t8zI93H064FGTz6w28x4fJ2Rosj//sZ LY6vDXdg9rhzbQ+bx41XC5k8Pm+SC2CO4rJJSc3JLEst0rdL4Mq4+Poyc8Ea3opVp1uZGxib uLsYOTgkBEwkzn6I6WLkBDLFJC7cW8/WxcjFISSwjFHiyLbzzBAJE4mPx9eyg9hCAtMZJS4c EYUo+sMo8fxpLytIgk1AS+LvmzfMIENFBLwl3l01AAkzC8hKXNx/lRGi103iSc8SNhCbU4BH Yt2fTrD5wgKeEr1bX4PFWQRUJfYfnQs2hlfAVuLrCg+QMK+AoMSPyfdYQMLMAuoSU6bkQkyX l9i85i0zxCfqEo/+6kLst5LommkIUSEise/FO0aIP3axSzRO84bYIyDxbfIhFohOWYlNB6Be lZQ4uOIGywRGiVlI1s5CWDsLydpZSBYsYGRZxSiaWpBcUJyUXmSqV5yYW1yal66XnJ+7iRES cRN3MN4/YH2IMRlo+0RmKdHkfGDE5pXEGxqbGVmYmpgaG5lbmpEmrCTOm/4oKUhIID2xJDU7 NbUgtSi+qDQntfgQIxMHp1QDo/YCtmTtgA9//Qod9t1KvWPCd+DItIC/Ry5sleKSn1aW+fNI UbHydbn/vD3iBXInm1Lv1FzycirUjVc+kjGv5MCsYsGKVS/evJk5x6Ch6YrH5yjeP2LsF3LY t5RU7nHIV2Z0O7oi3tPl3tIdETkJ3N073swt0BPNM7h59YGtP8OFHS1PE7b2KrEUZyQaajEX FScCAGWaKhvOAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFKsWRmVeSWpSXmKPExsVy+t9jQd3H064FGRx8zm0x4fJ2Rosj//sZ LY6vDXdg9rhzbQ+bx41XC5k8Pm+SC2COamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDU NbS0MFdSyEvMTbVVcvEJ0HXLzAFapKRQlphTChQKSCwuVtK3wzQhNMRN1wKmMULXNyQIrsfI AA0krGPMuPj6MnPBGt6KVadbmRsYm7i7GDk5JARMJD4eX8sOYYtJXLi3ng3EFhKYzihx4Yho FyMXkP2HUeL5015WkASbgJbE3zdvmLsYOThEBLwl3l01AAkzC8hKXNx/lRGi103iSc8SsDmc AjwS6/50MoPYwgKeEr1bX4PFWQRUJfYfnQs2hlfAVuLrCg+QMK+AoMSPyfdYQMLMAuoSU6bk QkyXl9i85i1YtQRQ+NFfXYj9VhJdMw0hKkQk9r14xziBUWgWkjmzEObMQjJnFpKOBYwsqxhF UwuSC4qT0nMN9YoTc4tL89L1kvNzNzGCY/qZ1A7GlQ0WhxgFOBiVeHh/hF8NEmJNLCuuzD3E KMHBrCTCq5l7LUiINyWxsiq1KD++qDQntfgQYzLQkxOZpUST84HpJq8k3tDYxMzI0sjMwsjE 3Jw0YSVx3gOt1oFCAumJJanZqakFqUUwW5g4OKUaGNPuPmO9wjal+8ufqxs48lWYGA8cNvnz SWs2u3YtXx57SOjiGY9LFa8cXX8kTb/rYr2NjQRXyOH10x3fJvc6VylorLMNvazCpPbt4a0H m+9ZqU88u+FuyfwdiV2lvgwXhANm6zC2zI4wu3qB7SH7tFirl6edL5xdtE9hQeMpFWGLIi87 zQu+05VYijMSDbWYi4oTAcv4rpMtAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change distinguishes DDR timing mode of current mixed usage to clarify device type. Signed-off-by: Seungwon Jeon Acked-by: Ulf Hansson --- drivers/mmc/core/debugfs.c | 3 +++ drivers/mmc/core/mmc.c | 2 +- include/linux/mmc/host.h | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 54829c0..509229b 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data) case MMC_TIMING_UHS_DDR50: str = "sd uhs DDR50"; break; + case MMC_TIMING_MMC_DDR52: + str = "mmc DDR52"; + break; case MMC_TIMING_MMC_HS200: str = "mmc high-speed SDR200"; break; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 98e9eb0..6d91ff7 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1261,7 +1261,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, goto err; } mmc_card_set_ddr_mode(card); - mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50); + mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52); mmc_set_bus_width(card->host, bus_width); } } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 99f5709..87b1f4f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -58,7 +58,8 @@ struct mmc_ios { #define MMC_TIMING_UHS_SDR50 5 #define MMC_TIMING_UHS_SDR104 6 #define MMC_TIMING_UHS_DDR50 7 -#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 #define MMC_SDR_MODE 0 #define MMC_1_2V_DDR_MODE 1