| Message ID | 002301cf11fb$cad390c0$607ab240$%jun@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 15 January 2014 15:12, Seungwon Jeon <tgih.jun@samsung.com> wrote: > Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS. > > CC: Wei WANG <wei_wang@realsil.com.cn> > CC: Samuel Ortiz <sameo@linux.intel.com> > Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> > --- > drivers/mmc/host/rtsx_pci_sdmmc.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c > index c46feda..752f003 100644 > --- a/drivers/mmc/host/rtsx_pci_sdmmc.c > +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c > @@ -864,6 +864,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) > rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); > break; > > + case MMC_TIMING_MMC_DDR52: > case MMC_TIMING_UHS_DDR50: > rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, > 0x0C | SD_ASYNC_FIFO_NOT_RST, > @@ -944,6 +945,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > host->vpclk = true; > host->double_clk = false; > break; > + case MMC_TIMING_MMC_DDR52: > case MMC_TIMING_UHS_DDR50: > case MMC_TIMING_UHS_SDR25: > host->ssc_depth = RTSX_SSC_DEPTH_1M; > -- > 1.7.0.4 > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c index c46feda..752f003 100644 --- a/drivers/mmc/host/rtsx_pci_sdmmc.c +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c @@ -864,6 +864,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); break; + case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST, @@ -944,6 +945,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) host->vpclk = true; host->double_clk = false; break; + case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: case MMC_TIMING_UHS_SDR25: host->ssc_depth = RTSX_SSC_DEPTH_1M;
Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS. CC: Wei WANG <wei_wang@realsil.com.cn> CC: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> --- drivers/mmc/host/rtsx_pci_sdmmc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)