diff mbox

[6/7] mmc: dw_mmc: clarify DDR timing mode between SD-UHS and eMMC

Message ID 002401cf11fb$ce4c3cc0$6ae4b640$%jun@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Seungwon Jeon Jan. 15, 2014, 2:12 p.m. UTC
Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50
is removed because of non-implementation of UHS signaling.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
---
 drivers/mmc/host/dw_mmc-exynos.c |    3 +--
 drivers/mmc/host/dw_mmc.c        |    2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

Comments

Ulf Hansson Jan. 16, 2014, 10:37 a.m. UTC | #1
On 15 January 2014 15:12, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50
> is removed because of non-implementation of UHS signaling.
>
> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>

> ---
>  drivers/mmc/host/dw_mmc-exynos.c |    3 +--
>  drivers/mmc/host/dw_mmc.c        |    2 +-
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index 3423c5e..b5a36b1 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
>
>  /* Common capabilities of Exynos4/Exynos5 SoC */
>  static unsigned long exynos_dwmmc_caps[4] = {
> -       MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
> -               MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
> +       MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
>         MMC_CAP_CMD23,
>         MMC_CAP_CMD23,
>         MMC_CAP_CMD23,
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index a776f24..99390bb 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>         regs = mci_readl(slot->host, UHS_REG);
>
>         /* DDR mode set */
> -       if (ios->timing == MMC_TIMING_UHS_DDR50)
> +       if (ios->timing == MMC_TIMING_MMC_DDR52)
>                 regs |= ((0x1 << slot->id) << 16);
>         else
>                 regs &= ~((0x1 << slot->id) << 16);
> --
> 1.7.0.4
>
>
> --
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diff mbox

Patch

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 3423c5e..b5a36b1 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -386,8 +386,7 @@  static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
 
 /* Common capabilities of Exynos4/Exynos5 SoC */
 static unsigned long exynos_dwmmc_caps[4] = {
-	MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
-		MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 	MMC_CAP_CMD23,
 	MMC_CAP_CMD23,
 	MMC_CAP_CMD23,
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a776f24..99390bb 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -962,7 +962,7 @@  static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	regs = mci_readl(slot->host, UHS_REG);
 
 	/* DDR mode set */
-	if (ios->timing == MMC_TIMING_UHS_DDR50)
+	if (ios->timing == MMC_TIMING_MMC_DDR52)
 		regs |= ((0x1 << slot->id) << 16);
 	else
 		regs &= ~((0x1 << slot->id) << 16);