From patchwork Wed Jan 15 14:12:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3492011 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7CAC8C02DC for ; Wed, 15 Jan 2014 14:13:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 745AD20122 for ; Wed, 15 Jan 2014 14:13:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3404920165 for ; Wed, 15 Jan 2014 14:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751918AbaAOOM5 (ORCPT ); Wed, 15 Jan 2014 09:12:57 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:57239 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751970AbaAOOMy (ORCPT ); Wed, 15 Jan 2014 09:12:54 -0500 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MZG007WE4SLXE50@mailout2.samsung.com> for linux-mmc@vger.kernel.org; Wed, 15 Jan 2014 23:12:21 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.50]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 11.D5.09028.54796D25; Wed, 15 Jan 2014 23:12:21 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-00-52d69745dec9 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 30.83.29263.54796D25; Wed, 15 Jan 2014 23:12:21 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MZG00C3E4SLQ1A0@mmp2.samsung.com>; Wed, 15 Jan 2014 23:12:21 +0900 (KST) From: Seungwon Jeon To: 'Chris Ball' , 'Jaehoon Chung' Cc: linux-mmc@vger.kernel.org References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> In-reply-to: Subject: [PATCH 6/7] mmc: dw_mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Wed, 15 Jan 2014 23:12:21 +0900 Message-id: <002401cf11fb$ce4c3cc0$6ae4b640$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22A= Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t8zI13X6deCDBbsFbWYcHk7o8WNX22s Fkf+9zM6MHvceLWQyaNvyypGj8+b5AKYo7hsUlJzMstSi/TtErgylr47z1gwibviVE8DSwPj Ks4uRk4OCQETiRnXLjNC2GISF+6tZ+ti5OIQEljGKNF/8hhLFyMHWNGvebYQ8emMEt/OPGAD aRAS+MMoMb/LHMRmE9CS+PvmDTOILSLgK3H2/wN2EJtZQFbi4v6rjBD1bhJPepaA9XIK8Eis +9MJVi8sECzRcG4TE4jNIqAqMWHhfbB6XgFbiXuL+5kgbEGJH5Pvgd3DLKAuMWVKLsR4eYnN a94yQ5ypLvHory6IKSJgJdE10xCiQkRi34t3jCDXSwgcYpfobPrLDLFJQOLb5ENQH8pKbDrA DAkFSYmDK26wTGCUmIVk7yyEvbOQ7J2FZMMCRpZVjKKpBckFxUnpRUZ6xYm5xaV56XrJ+bmb GCGR17eD8eYB60OMyUDbJzJLiSbnAyM3ryTe0NjMyMLUxNTYyNzSjDRhJXHeRQ+TgoQE0hNL UrNTUwtSi+KLSnNSiw8xMnFwSjUwii9deWXPel2m/fPPPJzN8Oh/zbSfFR9mr6lymLpiYnre NFcPts4Z0+denNCtvOpm/5kf597JSk5XsJvGauwUOn3HxCDpp3OfRL+NkGNf4ig2SVk8srzq +cNmrfM3kjwFfHSTjffvKbj7elHpPV0lRu3rTxcsfem8tmbZBYGam+Y6gXdvzIzN+6HEUpyR aKjFXFScCAD96/Jt0gIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsVy+t9jQV3X6deCDJ7/ErSYcHk7o8WNX22s Fkf+9zM6MHvceLWQyaNvyypGj8+b5AKYoxoYbTJSE1NSixRS85LzUzLz0m2VvIPjneNNzQwM dQ0tLcyVFPISc1NtlVx8AnTdMnOANikplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0Jgusx MkADCesYM5a+O89YMIm74lRPA0sD4yrOLkYODgkBE4lf82y7GDmBTDGJC/fWs3UxcnEICUxn lPh25gEbSEJI4A+jxPwucxCbTUBL4u+bN8wgtoiAr8TZ/w/YQWxmAVmJi/uvMkLUu0k86VkC 1sspwCOx7k8nWL2wQLBEw7lNTCA2i4CqxISF98HqeQVsJe4t7meCsAUlfky+xwJyG7OAusSU KbkQ4+UlNq95ywxxsrrEo7+6IKaIgJVE10xDiAoRiX0v3jFOYBSahWTOLIQ5s5DMmYWkYwEj yypG0dSC5ILipPRcQ73ixNzi0rx0veT83E2M4Lh+JrWDcWWDxSFGAQ5GJR7eH+FXg4RYE8uK K3MPMUpwMCuJ8GrmXgsS4k1JrKxKLcqPLyrNSS0+xJgM9OVEZinR5HxgyskriTc0NjEzsjQy szAyMTcnTVhJnPdAq3WgkEB6YklqdmpqQWoRzBYmDk6pBsY1/d+e2KovmSHw9HFLiQzX/+lM wXKWplfZVyXZr4tv01q+sum88vqbc0rPP12a/zy8ZMoptf3dD2+sYE1x8t7/3pmx7PiLvYsy JB/4nLgcJ6ayeQGnu3jY2cP96eX+L38HWkx4J3ppYtO79F3GH54FNV51+l/BUdI5Wym9zz5/ XcKat+UMYaZKLMUZiYZazEXFiQCOYZunLwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50 is removed because of non-implementation of UHS signaling. Signed-off-by: Seungwon Jeon Reviewed-by: Ulf Hansson --- drivers/mmc/host/dw_mmc-exynos.c | 3 +-- drivers/mmc/host/dw_mmc.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3423c5e..b5a36b1 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, /* Common capabilities of Exynos4/Exynos5 SoC */ static unsigned long exynos_dwmmc_caps[4] = { - MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, + MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index a776f24..99390bb 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) regs = mci_readl(slot->host, UHS_REG); /* DDR mode set */ - if (ios->timing == MMC_TIMING_UHS_DDR50) + if (ios->timing == MMC_TIMING_MMC_DDR52) regs |= ((0x1 << slot->id) << 16); else regs &= ~((0x1 << slot->id) << 16);