From patchwork Fri Mar 14 12:12:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3832481 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C4BBCBF540 for ; Fri, 14 Mar 2014 12:12:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E5DFC20320 for ; Fri, 14 Mar 2014 12:12:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EA1F120306 for ; Fri, 14 Mar 2014 12:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754358AbaCNMMh (ORCPT ); Fri, 14 Mar 2014 08:12:37 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:44431 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754348AbaCNMMe (ORCPT ); Fri, 14 Mar 2014 08:12:34 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2F009AWDWYNK10@mailout2.samsung.com> for linux-mmc@vger.kernel.org; Fri, 14 Mar 2014 21:12:34 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.49]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 8D.71.10092.232F2235; Fri, 14 Mar 2014 21:12:34 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-ac-5322f2321a3f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id AA.DF.29263.132F2235; Fri, 14 Mar 2014 21:12:33 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N2F007OFDWX5220@mmp1.samsung.com>; Fri, 14 Mar 2014 21:12:33 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Ulf Hansson' , 'Guennadi Liakhovetski' References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> <006301cf2a57$81fa0040$85ee00c0$%jun@samsung.com> In-reply-to: Subject: [PATCH RESEND v3 4/7] mmc: sh_mmcif: clarify DDR timing mode between SD-UHS and eMMC Date: Fri, 14 Mar 2014 21:12:33 +0900 Message-id: <003601cf3f7e$ae308bc0$0a91a340$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; 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CC: Guennadi Liakhovetski Signed-off-by: Seungwon Jeon --- drivers/mmc/host/sh_mmcif.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 54730f4..656fbba 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -803,12 +803,13 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, break; } switch (host->timing) { - case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: /* * MMC core will only set this timing, if the host - * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF - * implementations with this capability, e.g. sh73a0, - * will have to set it in their platform data. + * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR + * capability. MMCIF implementations with this + * capability, e.g. sh73a0, will have to set it + * in their platform data. */ tmp |= CMD_SET_DARS; break;