From patchwork Sat Feb 15 14:08:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3656411 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 542CE9F334 for ; Sat, 15 Feb 2014 14:08:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56B76201DE for ; Sat, 15 Feb 2014 14:08:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1283A201C8 for ; Sat, 15 Feb 2014 14:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753177AbaBOOIw (ORCPT ); Sat, 15 Feb 2014 09:08:52 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:44244 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753046AbaBOOIv (ORCPT ); Sat, 15 Feb 2014 09:08:51 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N11005YSJAQ9640@mailout2.samsung.com> for linux-mmc@vger.kernel.org; Sat, 15 Feb 2014 23:08:50 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.47]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id ED.7B.10092.2F47FF25; Sat, 15 Feb 2014 23:08:50 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-38-52ff74f2c917 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9D.98.29263.2F47FF25; Sat, 15 Feb 2014 23:08:50 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1100GEZJAQ7T70@mmp2.samsung.com>; Sat, 15 Feb 2014 23:08:50 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Ulf Hansson' References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> In-reply-to: Subject: [PATCH v2 1/7] mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Sat, 15 Feb 2014 23:08:50 +0900 Message-id: <006001cf2a57$73a07290$5ae157b0$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22AGGVY+QA== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsVy+t8zfd1PJf+DDKb1K1pMuLyd0eLI/35G i+Nrwx2YPe5c28PmcePVQiaPz5vkApijuGxSUnMyy1KL9O0SuDLmHz/PVnCHt2L7lgVMDYxr ubsYOTkkBEwkPt27yQJhi0lcuLeerYuRi0NIYBmjRNfdJmaYorst/9lAbCGB6YwSl+czQxT9 YZR4+bGPHSTBJqAl8ffNG7AGEQFZiZ9/LoA1MAt4S5z5PIUZotlN4knPErA4pwCPxLo/nWBx YQEfiYlfGphAbBYBVYkvkyDivAK2Ett+TmOCsAUlfky+B3QpB9BMdYkpU3IhxstLbF7zlhkk LAEUfvRXF+ICJ4nrn5ewQJSISOx78Y4R5GQJgV3sEo+2XWeFWCUg8W3yIRaIXlmJTQeg3pWU OLjiBssERolZSBbPQlg8C8niWUg2LGBkWcUomlqQXFCclF5krFecmFtcmpeul5yfu4kREnv9 OxjvHrA+xJgMtH0is5Rocj4wdvNK4g2NzYwsTE1MjY3MLc1IE1YS573/MClISCA9sSQ1OzW1 ILUovqg0J7X4ECMTB6dUA6PLSW7H8mVLTz9YtPBi+hSP3pd/Zsx7arH8XEG9/+GDN9gCZnkf XOa6IOPjKyXfo6/F4rbVbd7EvlbqxpIE/rBewWk+Get3z/5k9qi/ZK6e1Bed9bJKHnMb+H4J nr5ukdetIfsltNQ9OGX1jdNWfV3KkRn6gknOH6snvitMKFR5/eNoF+OixkIlluKMREMt5qLi RADdV9L30wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLKsWRmVeSWpSXmKPExsVy+t9jQd1PJf+DDHask7WYcHk7o8WR//2M FsfXhjswe9y5tofN48arhUwenzfJBTBHNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjq GlpamCsp5CXmptoqufgE6Lpl5gAtUlIoS8wpBQoFJBYXK+nbYZoQGuKmawHTGKHrGxIE12Nk gAYS1jFmzD9+nq3gDm/F9i0LmBoY13J3MXJySAiYSNxt+c8GYYtJXLi3HswWEpjOKHF5PnMX IxeQ/YdR4uXHPnaQBJuAlsTfN2+YQWwRAVmJn38ugDUwC3hLnPk8hRmi2U3iSc8SsDinAI/E uj+dYHFhAR+JiV8amEBsFgFViS+TIOK8ArYS235OY4KwBSV+TL7H0sXIATRTXWLKlFyI8fIS m9e8ZQYJSwCFH/3VhbjASeL65yUsECUiEvtevGOcwCg0C8mgWQiDZiEZNAtJxwJGllWMoqkF yQXFSem5hnrFibnFpXnpesn5uZsYwZH9TGoH48oGi0OMAhyMSjy8Err/goRYE8uKK3MPMUpw MCuJ8IYl/A8S4k1JrKxKLcqPLyrNSS0+xJgM9OZEZinR5Hxg0skriTc0NjEzsjQyszAyMTcn TVhJnPdAq3WgkEB6YklqdmpqQWoRzBYmDk6pBsZYtnVvRY4mOU7UPTsxYNbKnPPHartOm6U2 p704eG7rlAfyqw+fWhXc0p3QsOnGK2s3ji3XQ12Eb2vIL3q1pNV2ainbo2yRXWrVZWwCx0PM Jl/7kbPdcvXtq7ddvp4UD9vwYNPcq00x+zYzXVZbdOXfFqYHPCkzPyyctHy///dZHxd8+bLi f4XlaSWW4oxEQy3mouJEAOztPWwwAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change distinguishes DDR timing mode of current mixed usage to clarify device type. Signed-off-by: Seungwon Jeon Acked-by: Ulf Hansson --- drivers/mmc/core/debugfs.c | 3 +++ drivers/mmc/core/mmc.c | 2 +- include/linux/mmc/host.h | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 54829c0..509229b 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data) case MMC_TIMING_UHS_DDR50: str = "sd uhs DDR50"; break; + case MMC_TIMING_MMC_DDR52: + str = "mmc DDR52"; + break; case MMC_TIMING_MMC_HS200: str = "mmc high-speed SDR200"; break; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 98e9eb0..6d91ff7 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1261,7 +1261,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, goto err; } mmc_card_set_ddr_mode(card); - mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50); + mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52); mmc_set_bus_width(card->host, bus_width); } } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 99f5709..87b1f4f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -58,7 +58,8 @@ struct mmc_ios { #define MMC_TIMING_UHS_SDR50 5 #define MMC_TIMING_UHS_SDR104 6 #define MMC_TIMING_UHS_DDR50 7 -#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 #define MMC_SDR_MODE 0 #define MMC_1_2V_DDR_MODE 1