From patchwork Sat Feb 15 14:09:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3656461 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7F390BF13A for ; Sat, 15 Feb 2014 14:09:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD72C201C8 for ; Sat, 15 Feb 2014 14:09:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEF9A20172 for ; Sat, 15 Feb 2014 14:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753251AbaBOOJ0 (ORCPT ); Sat, 15 Feb 2014 09:09:26 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:44282 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753046AbaBOOJZ (ORCPT ); Sat, 15 Feb 2014 09:09:25 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N11000JBJBOTN60@mailout2.samsung.com> for linux-mmc@vger.kernel.org; Sat, 15 Feb 2014 23:09:24 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.47]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 5A.8B.10092.4157FF25; Sat, 15 Feb 2014 23:09:24 +0900 (KST) X-AuditID: cbfee68f-b7f156d00000276c-bf-52ff751457ee Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id F0.5C.28157.4157FF25; Sat, 15 Feb 2014 23:09:24 +0900 (KST) Received: from DOTGIHJUN01 ([12.23.118.161]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N11008RVJBOQBA0@mmp1.samsung.com>; Sat, 15 Feb 2014 23:09:24 +0900 (KST) From: Seungwon Jeon To: linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Jaehoon Chung' References: <1383653403-10049-1-git-send-email-ulf.hansson@linaro.org> In-reply-to: Subject: [PATCH v2 6/7] mmc: dw_mmc: clarify DDR timing mode between SD-UHS and eMMC Date: Sat, 15 Feb 2014 23:09:25 +0900 Message-id: <006501cf2a57$881b0ff0$98512fd0$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac7aH/uUm1J6MxFOSyaXb4Fx/nx/rAABnFmgDfJZ22AGGaDjEA== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrIIsWRmVeSWpSXmKPExsVy+t8zfV2R0v9BBhM3mltMuLyd0eLGrzZW iyP/+xkdmD1uvFrI5NG3ZRWjx+dNcgHMUVw2Kak5mWWpRfp2CVwZBz8uYCw4yl2xa+Fd9gbG G5xdjJwcEgImEnPOvGWFsMUkLtxbz9bFyMUhJLCMUeLY9hcsMEUdTzeA2UICixglvkzLgSj6 wyix+eV+sG42AS2Jv2/eMIPYIgKyEj//XGADsZkFfCUWfJ/OBNHsJvGkZwlYnFOAR2Ldn06w emGBMImGX/8YQWwWAVWJicd6wWp4BWwl2rYsZ4GwBSV+TL4HZHMAzVSXmDIlF2K8vMTmNW+Z QcISQOFHf3UhLnCSOPJ4EgtEiYjEvhfvGEFOlhDYxy7xbe1jqFUCEt8mH2KB6JWV2HSAGeJd SYmDK26wTGCUmIVk8SyExbOQLJ6FZMMCRpZVjKKpBckFxUnpRcZ6xYm5xaV56XrJ+bmbGCHR 17+D8e4B60OMyUDbJzJLiSbnA6M3ryTe0NjMyMLUxNTYyNzSjDRhJXHe+w+TgoQE0hNLUrNT UwtSi+KLSnNSiw8xMnFwSjUwZqtx7tsq58ZWWnxl7TrWP9sOnbwvnS92V3fD+4JXoRX39jbv yxTr/FZaVSpyIP2mwOZHH7Wy92eV164zfnFEq7a0f+bhhOqOGaa37sy2qr5WFGEuVeFu6mrJ rVJ7kd1Q6Ix39Cm3c6WW8WXJj1xSHfqVnFn3WO5+snuCp/0n+4MFLXZik5YosRRnJBpqMRcV JwIAVAXX1NQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsVy+t9jAV2R0v9BBn0vjS0mXN7OaHHjVxur xZH//YwOzB43Xi1k8ujbsorR4/MmuQDmqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwND XUNLC3MlhbzE3FRbJRefAF23zBygTUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqM DNBAwjrGjIMfFzAWHOWu2LXwLnsD4w3OLkZODgkBE4mOpxtYIGwxiQv31rOB2EICixglvkzL 6WLkArL/MEpsfrmfFSTBJqAl8ffNG2YQW0RAVuLnnwtgDcwCvhILvk9ngmh2k3jSswQszinA I7HuTydYvbBAmETDr3+MIDaLgKrExGO9YDW8ArYSbVuWs0DYghI/Jt8DsjmAZqpLTJmSCzFe XmLzmrfMIGEJoPCjv7oQFzhJHHk8iQWiRERi34t3jBMYhWYhGTQLYdAsJINmIelYwMiyilE0 tSC5oDgpPddIrzgxt7g0L10vOT93EyM4tp9J72Bc1WBxiFGAg1GJh1dC91+QEGtiWXFl7iFG CQ5mJRHesIT/QUK8KYmVValF+fFFpTmpxYcYk4HenMgsJZqcD0w7eSXxhsYmZkaWRmYWRibm 5qQJK4nzHmy1DhQSSE8sSc1OTS1ILYLZwsTBKdXA6JF2zU3X9kX/q+SfLy9Vpt/7kd7tsPOf KOtqg4VTjX41O+lEvU31Pr/9ttHLS/+S9l+1WW27Y6dJV/O0zzEpsc1nzNcouhx/Kcm7pOzL C80LUxiYnj2/fTi553HZv21Hph9uiuPItlve7PE19Wq61O5L6mK3lF+HHDY/Nudw3kHmc+X7 7XiPTFJiKc5INNRiLipOBACh2bEgMQMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50 is removed because of non-implementation of UHS signaling. Signed-off-by: Seungwon Jeon Reviewed-by: Ulf Hansson --- drivers/mmc/host/dw_mmc-exynos.c | 3 +-- drivers/mmc/host/dw_mmc.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3423c5e..b5a36b1 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, /* Common capabilities of Exynos4/Exynos5 SoC */ static unsigned long exynos_dwmmc_caps[4] = { - MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, + MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 55cd110..7866d78 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) regs = mci_readl(slot->host, UHS_REG); /* DDR mode set */ - if (ios->timing == MMC_TIMING_UHS_DDR50) + if (ios->timing == MMC_TIMING_MMC_DDR52) regs |= ((0x1 << slot->id) << 16); else regs &= ~((0x1 << slot->id) << 16);